31.6.1 Principle of Operation
The basic structure of the SERCOM serial engine is shown in the following figure. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock.
The transmitter consists of a single write buffer and a Shift register.
The receiver consists of a one-level (I2C), or two-level (USART, SPI) receive buffer and a Shift register.
The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock.
Address matching logic is included for SPI and I2C operation.