16.6.7 APBA Mask

Name: APBAMASK
Offset: 0x14
Reset: 0x000007FF
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 TC1TC0SERCOM1SERCOM0FREQMEICRTCWDT 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000111 
Bit 76543210 
 GCLKSUPCOSC32KCTRLOSCCTRLRSTCMCLKPMPAC 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 14, 15 – TCn TCn APBA Clock Enable

ValueDescription
0 The APBA clock for the TCn is stopped.
1 The APBA clock for the TCn is enabled.

Bits 12, 13 – SERCOM SERCOMn APBA Clock Enable

ValueDescription
0 The APBA clock for the SERCOMn is stopped.
1 The APBA clock for the SERCOMn is enabled.

Bit 11 – FREQM FREQM APBA Clock Enable

ValueDescription
0 The APBA clock for the FREQM is stopped.
1 The APBA clock for the FREQM is enabled.

Bit 10 – EIC EIC APBA Clock Enable

ValueDescription
0 The APBA clock for the EIC is stopped.
1 The APBA clock for the EIC is enabled.

Bit 9 – RTC RTC APBA Clock Enable

ValueDescription
0 The APBA clock for the RTC is stopped.
1 The APBA clock for the RTC is enabled.

Bit 8 – WDT WDT APBA Clock Enable

ValueDescription
0 The APBA clock for the WDT is stopped.
1 The APBA clock for the WDT is enabled.

Bit 7 – GCLK GCLK APBA Clock Enable

ValueDescription
0 The APBA clock for the GCLK is stopped.
1 The APBA clock for the GCLK is enabled.

Bit 6 – SUPC SUPC APBA Clock Enable

ValueDescription
0 The APBA clock for the SUPC is stopped.
1 The APBA clock for the SUPC is enabled.

Bit 5 – OSC32KCTRL OSC32KCTRL APBA Clock Enable

ValueDescription
0 The APBA clock for the OSC32KCTRL is stopped.
1 The APBA clock for the OSC32KCTRL is enabled.

Bit 4 – OSCCTRL OSCCTRL APBA Clock Enable

ValueDescription
0 The APBA clock for the OSCCTRL is stopped.
1 The APBA clock for the OSCCTRL is enabled.

Bit 3 – RSTC RSTC APBA Clock Enable

ValueDescription
0 The APBA clock for the RSTC is stopped.
1 The APBA clock for the RSTC is enabled.

Bit 2 – MCLK MCLK APBA Clock Enable

ValueDescription
0 The APBA clock for the MCLK is stopped.
1 The APBA clock for the MCLK is enabled.

Bit 1 – PM PM APBA Clock Enable

ValueDescription
0 The APBA clock for the PM is stopped.
1 The APBA clock for the PM is enabled.

Bit 0 – PAC PAC APBA Clock Enable

ValueDescription
0 The APBA clock for the PAC is stopped.
1 The APBA clock for the PAC is enabled.