45.7.18 Compare/Capture Channel x
The CCx register represents the 16-bit and 24- bit value, CCx. The register has two functions, depending of the mode of operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms.
The CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx
register synchronization is complete.
| Name: | CC |
| Offset: | 0x44 + n*0x04 [n=0..5] |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CC[17:10] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CC[9:2] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CC[1:0] | DITHER[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:6 – CC[17:0] Channel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note:
- When the TCC is configured as a 16-bit timer/counter, the excess bits are read as zero.
- This bit field occupies the MSB
of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [23:m] 0x0 - NONE 23:0 0x1 - DITH4 23:4 0x2 - DITH5 23:5 0x3 - DITH6 23:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
Note: This bit field consists of the n LSB
of the register. n is dependent on the value of the Resolution bits in the Control A
register (CTRLA.RESOLUTION):
| CTRLA.RESOLUTION | Bits [n:0] |
|---|---|
| 0x0 - NONE | - |
| 0x1 - DITH4 | 3:0 |
| 0x2 - DITH5 | 4:0 |
| 0x3 - DITH6 | 5:0 (depicted) |