38.8.45 Tx Event FIFO Configuration

This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
Name: TXEFC
Offset: 0xF0
Reset: 0x00000000
Property: Write-restricted

Bit 3130292827262524 
   EFWM[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
   EFS[5:0] 
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
 EFSA[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 EFSA[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 29:24 – EFWM[5:0] Event FIFO Watermark

ValueDescription
0 Watermark interrupt disabled.
1 - 32 Level for Tx Event FIFO watermark interrupt (IR.TEFW).
>32 Watermark interrupt disabled.

Bits 21:16 – EFS[5:0] Event FIFO Size

The Tx Event FIFO elements are indexed from 0 to EFS - 1.
ValueDescription
0 Tx Event FIFO disabled
1 - 32 Number of Tx Event FIFO elements.
>32 Values greater than 32 are interpreted as 32.

Bits 15:0 – EFSA[15:0] Event FIFO Start Address

Start address of Tx Event FIFO in Message RAM. When the CAN module addresses the Message RAM it addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses, i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. Bits 1 to 0 will always be read back as “00”.