42.7.4 Event Control
| Name: | EVCTRL |
| Offset: | 0x06 |
| Reset: | 0x0000 |
| Property: | Enable-Protected, PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MCEO1 | MCEO0 | VLCEO | DIREO | ERREO | OVFEO | ||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVEI2 | EVEI1 | EVEI0 | EVINV2 | EVINV1 | EVINV0 | EVACT[1:0] | |||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 12, 13 – MCEOx Match Channel x Event Output Enable
These bits control whether event match on channel x is enabled or not and generated for every match.
| Value | Description |
|---|---|
| 0 | Match event on channel x is disabled and will not be generated. |
| 1 | Match event on channel x is enabled and will be generated for every compare. |
Bit 11 – VLCEO Velocity Output Event Enable
This bit is used to enable the velocity event. When enabled, an event level will be generated for each change on the qualified PDEC phases.
This bit has no effect when COUNTER operation mode is selected.
| Value | Description |
|---|---|
| 0 | VLC output event is disabled and will not be generated. |
| 1 | VLC output is enabled and will be generated for every valid velocity condition. |
Bit 10 – DIREO Direction Output Event Enable
This bit is used to enable the Direction event. When enabled, an event level output is generated to report the rotation direction.
| Value | Description |
|---|---|
| 0 | DIR output event is disabled and will not be generated. |
| 1 | DIR output is enabled and changes the level when the rotation direction changes. |
Bit 9 – ERREO Error Output Event Enable
| Value | Description |
|---|---|
| 0 | ERR Event output is disabled. |
| 1 | ERR Event output is enabled. |
Bit 8 – OVFEO Overflow/Underflow Output Event Enable
This bit is used to enable the Overflow/Underflow event. When enabled, an event will be generated when the Counter overflows/underflows.
| Value | Description |
|---|---|
| 0 | Overflow/Underflow event is disabled and will not be generated. |
| 1 | Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow. |
Bits 5, 6, 7 – EVEIx Event x Input Enable
This bit is used to enable asynchronous input event x to the counter.
| Value | Description |
|---|---|
| 0 | Incoming event x is disabled. |
| 1 | Incoming event x is enabled. |
Bits 2, 3, 4 – EVINVx Inverted Event x Input Enable
This bit inverts the asynchronous input event x to the counter.
| Value | Description |
|---|---|
| 0 | Input event source x is not inverted. |
| 1 | Input event source x is inverted. |
Bits 1:0 – EVACT[1:0] Event Action
These bits have an effect only when COUNTER operation mode is selected, and ignored in all other operation modes.
These bits define the event action the counter will perform on an event.
| Value | Name | Description |
|---|---|---|
| 0 | OFF | Event action disabled |
| 1-3 | Reserved | - |