11.3 Electrical Pinout

Table 11-4. TFBGA81 Electrical Pinout
Pin No Pin Name I/O I(mA) Res HY Pin No Pin Name I/O I(mA) Res HY
A1 GND P E6 NC
A2 TXRX1 I/O ±2/4 PU/PD/- Y/- E7 NC
A3 EMIT3 OT ±60(1) E8 ASI1 I/O ±2/4 PU/PD/- Y/-
A4 EMIT2 OT ±60(1) E9 ASI0 I/O ±2/4 PU/PD/- Y/-
A5 VREGP (6) F1 VDDIN_AN P
A6 PVDDAMP P F2 VREFP (6)
A7 OUT O ±1500 (2) F3 AGND P
A8 ASO1 O 1200 (3) F4 GND P
A9 PGND P F5 VDDIO P
B1 AGC OT ±20 (4) PU/- F6 VDDIO P
B2 GND P F7 THW1 I/O ±2/4 PU/PD/- Y/-
B3 EMIT3 OT ±60(1) F8 NTHW0 I/O ±2/4 PU/PD/- Y/-
B4 EMIT2 OT ±60(1) F9 MISO I/O ±2/4 PU/PD/- Y/-
B5 VREGN (6) G1 VREFC (6)
B6 PVDDAMP P G2 VREFN (6)
B7 OUT O ±1500 (2) G3 NRST I Y
B8 ASO1 O 1200 (3) G4 VDDIO
B9 PGND P G5 GND
C1 VDDCORE P G6 VDDIO P
C2 VDDCORE P G7 G1 I/O ±2/4 PU/PD/- Y/-
C3 GND P G8 CS I/O ± 2/4 PU/PD/- Y/-
C4 GND P G9 MOSI I/O ± 2/4 PU/PD/- Y/-
C5 GND P H1 VDDIN_AN P
C6 GNDAMP P H2 STBY I Y
C7 VDDAMP P H3 XIN I
C8 PGND P H4 GND P
C9 ASO0 O 1200 (3) H5 VDDCORE P
D1 VDDIO P H6 VDDIN P
D2 VDDIO P H7 THEN I/O ±2/4 PU/PD/- Y/-
D3 VDDIO P H8 EXTIN I/O ± 2/4 PU/PD/- Y/-
D4 GND P H9 SCK I/O ± 2/4 PU/PD/- Y/-
D5 GND P J1 GND P
D6 NC J2 VZC I (5) Y
D7 GND P J3 XOUT O
D8 VDDAMP P J4 VDDPLL P
D9 ASO0 O 1200 (3) J5 VDDCORE P
E1 VIN I J6 VDDIN
E2 AGND P J7 ENABLE I Y
E3 GND P J8 TXEN I/O ±2/4 PU/PD/- Y/-
E4 VDDIO P J9 GND P
E5 NC
I/O = pin direction (I = input, O = output, T = tri-state, P = power)
I(mA) = nominal current (+ = source, - = sink)
Res = pin pull-up/pull-down resistor (PU = pull up, PD = pull down (70-140 kΩ, typical 100 kΩ))
HY = Input Hysteresis (Y = yes)
Notes:
  1. Maximum value considering the use of both balls per EMITx
  2. Maximum value considering the use of both balls of OUT
  3. Maximum value considering the use of both balls per ASOx
  4. Selectable from 5 mA to 20 mA in 4 steps of 5 mA
  5. In case of fuse programming, an external 10 kΩ serial resistor is needed (see 7.4.5 Fuse Programming).
  6. VREGP, VREGN, VREFP, VREFC and VREFN are analog signals.