4.3 Pinout Specification

Table 4-3. Pinout Specification
BalloutPower RailI/O TypePrimaryReset State
SignalDirSignal, Dir, Hiz, ST
A1GNDPowerGND
A2VDDIOGPIOTXRX1I/OPIO, I, Hiz
A3VDDIOPLCEMIT3OO, Hiz
A4VDDIOPLCEMIT2OO, Hiz
A5PVDDAMPPowerVREGP
A6PVDDAMPPowerPVDDAMP
A7PVDDAMPPLCOUTO
A8PVDDAMPPLCASO1O
A9PGNDPowerPGND
B1VDDIOAGCAGCOO, ST0
B2GNDPowerGND
B3VDDIOPLCEMIT3OO, Hiz
B4VDDIOPLCEMIT2OO, Hiz
B5PVDDAMPPowerVREGN
B6PVDDAMPPowerPVDDAMP
B7PVDDAMPPLCOUTO
B8PVDDAMPPLCASO1O
B9PGNDPowerPGND
C1VDDCOREPowerVDDCORE
C2VDDCOREPowerVDDCORE
C3GNDPowerGND
C4GNDPowerGND
C5GNDPowerGND
C6GNDAMPPowerGNDAMP
C7PVDDAMPPowerVDDAMP
C8PGNDPowerPGND
C9PVDDAMPPLCASO0O
D1VDDIOPowerVDDIO
D2VDDIOPowerVDDIO
D3VDDIOPowerVDDIO
D4GNDPowerGND
D5GNDPowerGND
D6NCDo not connect, reserved for test
D7GNDPowerGND
D8PVDDAMPPowerVDDAMP
D9PVDDAMPPLCASO0O
E1VDDIN_ANPLCVINII, Hiz
E2AGNDGroundAGND
E3GNDPowerGND
E4VDDIOPowerVDDIO
E5NCDo not connect, reserved for test
E6NCDo not connect, reserved for test
E7NCDo not connect, reserved for test
E8VDDIOGPIOASI1O
E9VDDIOGPIOASI0O
F1VDDIN_ANPowerVDDIN_AN
F2VDDIN_ANAnalogVREFP
F3AGNDPowerAGND
F4GNDPowerGND
F5VDDIOPowerVDDIO
F6VDDIOPowerVDDIO
F7VDDIOGPIOTHW1O
F8VDDIOGPIONTHW0O
F9VDDIOGPIOMISOI/OMISO, I, Hiz
G1VDDIN_ANAnalogVREFC
G2VDDIN_ANAnalogVREFN
G3VDDIORSTNRSTII, Hiz
G4VDDIOPowerVDDIO
G5GNDPowerGND
G6VDDIOPowerVDDIO
G7VDDIOGPIOG1IPIO, I, Hiz
G8VDDIOGPIOCSI/OCS, I, Hiz
G9VDDIOGPIOMOSII/OMOSI, I, Hiz
H1VDDIN_ANPowerVDDIN_AN
H2VDDIOGPIOSTBYI
H3VDDIOCLOCKXINII, Hiz
H4GNDPowerGND
H5VDDCOREPowerVDDCORE
H6VDDINPowerVDDIN
H7VDDIOGPIOTHENIPIO, I, Hiz
H8VDDIOGPIOEXTINOPIO, I, Hiz
H9VDDIOGPIOSCKI/OSCK, I, Hiz
J1GNDPowerGND
J2VDDIOGPIOVZCIVZC/PIO, I, Hiz
J3VDDIOCLOCKXOUTOO
J4VDDPLLPowerVDDPLL
J5VDDCOREPowerVDDCORE
J6VDDINPowerVDDIN
J7VDDIOLDOENABLEII, Hiz
J8VDDIOGPIOTXENIPIO, I, Hiz
J9GNDPowerGND
Note:

HiZ = High Impedance, ST = Set To