The PIC18F26/46/56Q83 devices that you have received conform functionally to the current device data sheet (DS40002253D), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.
The errata described in this document will be addressed in future revisions of the PIC18F26/46/56Q83 silicon.
Note: This document summarizes all silicon errata issues
from all revisions of silicon, previous as well as current.
| Part Number | Device ID | Revision ID | ||
|---|---|---|---|---|
| A1 | A2 | B0 | ||
| PIC18F26Q83 | 0xA306 | 0xA001 | 0xA002 | 0xA400 |
| PIC18F46Q83 | 0xA307 | 0xA001 | 0xA002 | 0xA400 |
| PIC18F56Q83 | 0xA308 | 0xA001 | 0xA002 | 0xA400 |
Important: Refer to the Device/Revision ID section
in the current “PIC18-Q83/84 Family Programming Specification” (DS40002137) for more
detailed information on Device Identification and Revision IDs for your specific
device.
| Module | Feature | Item No. | Issue Summary | Affected Revisions | ||
|---|---|---|---|---|---|---|
| A1 | A2 | B0 | ||||
| UTMR | Level-triggered ERS Start/Reset condition | Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access | Dead zone exists in level-triggered Start/Reset condition when ERS signal is generated due to an SFR access | X | X | X |
| Hardware Reset condition | Reset Does Not Happen at Period Match When the Prescaler > 0 and the Timer Stops at Period Match | Reset does not happen at period match when the prescaler > 0 and the Timer Stops at Period Match (includes One Shot mode) | X | X | X | |
| Output Pulse | 1.1.3 | Pulse output does not occur at period match when the prescaler > 0 | X | X | X | |
| Clear Command | Clear Command May Not Work Properly in Asynchronous Mode | Clear Command may not work properly | X | X | X | |
| I2C | Start and Stop Interrupt Function | The I2C Start and/or Stop Flags May Be Set When I2C Is Enabled | The I2C Start and/or Stop flags may be set when I2C is enabled | X | X | X |
| SMT | Reset Bit | Reset Bit | SMT Stops working if RST is set while prescaler setting is not zero | X | X | X |
| ADCC with Context | Double Sample Conversions | Double Sample Conversions | An unexpected acquisition time is added between the first and second conversion | X | X | X |
| PIC18 Core | FSR Shadow Registers | FSR Shadow Registers Are Not Writable | FSR shadow registers are not writable | X | X | X |
| UART | Stop bit | UART TXDE Signal May Go Low before the STOP Bit Has Been Entirely Transmitted | TXDE signal may go low before the STOP bit has been entirely transmitted | X | X | X |
| ICD | Single-Step Function (SSTEP) | Single Step Function Does Not Execute at SW Breakpoint | Single Step function does not execute at Software Breakpoint | X | X | X |
| PWM | PWM Mode | Wrong Duty Cycle for CCP Module | Wrong Duty Cycle for CCP Module | X | X | X |
| ICSP™ | Low-Voltage Programming (LVP) | Low-Voltage Programming Not Possible | Low-Voltage Programming is not possible when VDD is below BORV while BOR is enabled | X | X | X |
| CAN | Masks/Filters | Filters 8-11 Will Erroneously Accept Incoming Messages With SID of 0x000 | Filters 8-11 will erroneously accept incoming messages with SID of 0x000 | X | X | |
|
Note: Only those issues
indicated in the last column apply to the current silicon revision.
| ||||||