1.1.4 Clear Command May Not Work Properly in Asynchronous Mode
When operating in Asynchronous mode (CSYNC = 0), setting the Clear
Command bit (CLR= 1) may not clear the Timer Counter register
value.
Work Around
Use the Universal Timer module in Synchronous mode (CSYNC = 1) when
the Clear Command bit (CLR) is being used.
Affected Silicon Revisions
| A1 | A2 | B0 | |||||
| X | X | X |