16.3.2.3 Event Generators

Each event channel has several possible event generators, but only one can be selected at a time. The event generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn) register. By default, the channels are not connected to any event generator. For details on event generation, refer to the documentation of the corresponding peripheral.

A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous events can be generated outside the normal edges of the peripheral clock, making the system respond faster than the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a sleep mode when the peripheral clock is not running.

Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either synchronous or asynchronous, with properties according to the table below.

Table 16-1. Properties of Generated Events
Event Type Sync/Async Description
Pulse Sync An event generated from CLK_PER that lasts one clock cycle
Async An event generated from a clock other than CLK_PER lasting one clock cycle
Level Sync An event generated from CLK_PER that lasts multiple clock cycles
Async An event generated without a clock (for example, a pin or a comparator), or an event generated from a clock other than CLK_PER that lasts multiple clock cycles

The properties of both the generated event and the intended event user must be considered in order to ensure reliable and predictable operation.

The table below shows the available event generators for this device family.

Table 16-2. Event Generators
Generator Name Description Event Type Generating Clock Domain Length of event
Peripheral Event
UPDI SYNCH SYNCH character Level CLK_PDI SYNCH character on PDI RX input synchronized to CLK_PDI
MVIO VDDIO2OK VDDIO2 is OK Level Asynchronous High when VDDIO2 is OK
RTC OVF Overflow Pulse CLK_RTC One CLK_RTC period
CMP Compare Match
PIT_DIV8192 Prescaled RTC clock divided by 8192 Level Given by prescaled RTC clock divided by 8192
PIT_DIV4096 Prescaled RTC clock divided by 4096 Given by prescaled RTC clock divided by 4096
PIT_DIV2048 Prescaled RTC clock divided by 2048 Given by prescaled RTC clock divided by 2048
PIT_DIV1024 Prescaled RTC clock divided by 1024 Given by prescaled RTC clock divided by 1024
PIT_DIV512 Prescaled RTC clock divided by 512 Given by prescaled RTC clock divided by 512
PIT_DIV256 Prescaled RTC clock divided by 256 Given by prescaled RTC clock divided by 256
PIT_DIV128 Prescaled RTC clock divided by 128 Given by prescaled RTC clock divided by 128
PIT_DIV64 Prescaled RTC clock divided by 64 Given by prescaled RTC clock divided by 64
CCL LUTn LUT output level Level Asynchronous Depends on CCL configuration
ACn OUT Comparator output level Level Asynchronous Given by AC output level
ADCn RESRDY Result ready Pulse CLK_PER One CLK_PER period
ZCDn OUT ZCD output level Level Asynchronous Given by ZCD output level
OPAMPn READY Op amp ready Pulse CLK_PER One CLK_PER period
PORTx PINn Pin level Level Asynchronous Given by pin level
USARTn XCK USART Baud clock Level CLK_PER Minimum two CLK_PER periods
SPIn SCK SPI Host clock Level CLK_PER Minimum two CLK_PER periods
TCAn OVF_LUNF Overflow/Low byte timer underflow Pulse CLK_PER One CLK_PER period
HUNF High byte timer underflow
CMP0_LCMP0 Compare channel 0 match/Low byte timer compare channel 0 match
CMP1_LCMP1 Compare channel 1 match/Low byte timer compare channel 1 match
CMP2_LCMP2 Compare channel 2 match/Low byte timer compare channel 2 match
TCBn CAPT CAPT flag set Pulse CLK_PER One CLK_PER period
OVF Overflow
TCDn CMPBCLR Counter matches CMPBCLR Pulse CLK_TCD One CLK_TCD period
CMPASET Counter matches CMPASET
CMPBSET Counter matches CMPBSET
PROGEV Programmable event output