1 Known Issues and Change Log

LOGIC-34: Logic synthesis may fail when signals are optimised into constants

A logic design can fail to synthesize when it has an output signal that becomes optimized into a constant. Examples of this are a Look-up Table (LUT) symbol populated with 0x0000 or 0xFFFF values, a signal combined with its inverse or a constant 0 or 1 symbol.

Workaround: Use the zero input port as a constant source

LOGIC-48: It is not possible to change the interface of a module (sub-sheet) once it is used

Workaround: When the interface of a module (sub-sheet) is changed, it is necessary to delete all instances of the use of this module and place the module once more.

LOGIC-545: It is not possible to make use of all input synchronizer options as described in the data sheet.

Only synchronous, direct connection and rising/falling-edge detector options are currently available.

LOGIC-475: Timing information is unavailable

The synthesis and place-and-route processes do not take timing into consideration and no timing information is made available on the results of this process.

LOGIC-514: BELS output is unavailable

The toolchain does not currently produce a representation of the BELS layout after synthesis and place-and-route.

LOGIC-1071: Improved feedback to users from backend synthesis process

The CLB Synthesizer frontend GUI now includes a synthesis output tab which gives more detailed information when backend synthesis fails.

LOGIC-1165: Prevent synthesis when design errors are present

The Synthesis button is now disabled when design errors are present. This can be bypassed in the Preferences dialog for debugging purposes.

LOGIC-1099: Provide easier access to library modules

The CLB library on GitHub is now accessible through the drawer menu in the Library section.