1 Known Issues and Change Log

This section presents known issues, limitations and change logs for the Configurable Logic Block (CLB) Synthesizer.

The CLB Synthesizer toolchain is comprised of:

The synthesis engine (backend), hosted in the cloud
CLB Synthesizer GUI hosted in the cloud at logic.microchip.com/clbsynthesizer/
CLB Synthesizer GUI integrated into MPLAB® Code Configurator (MCC), deployed via MCC Content Manager

Releases are tracked in CalVer format. Components included in a release follow SemVer.

If available, include the ZIP archive from the synthesis process when contacting Microchip Support.

Known Issues and Limitations

LOGIC-34: Logic synthesis may fail when signals are optimized into constants

A logic design can fail to synthesize when it has an output signal that becomes optimized into a constant. Examples of this are a Look-up Table (LUT) symbol populated with 0x0000 or 0xFFFF values, a signal combined with its inverse, or a constant 0 or 1 symbol.

Workaround: Use the zero input port as a constant source
LOGIC-475: Timing information is unavailable

The synthesis and place-and-route processes do not consider timing, and no timing information is made available on the results of this process.

Simulator known issues:

LOGIC-2045: UART, PWM and SPI stimuli are missing start offset configuration (offset is always 0)
LOGIC-2055: It is not possible to use the simulator with designs, which use the built-in counter
LOGIC-2054: Internal nets and parameters are shown in the VCD viewer
LOGIC-1947: Changing clock frequency causes simulation cycles to change
LOGIC- 2086: A zero port (constant) should not require inputs from a test bench

Scope: Web frontend and synthesis backend

New features:

Scope: Web frontend and integrated MCC version

New features:

Bug fixes:

Scope: Synthesis backend, web version, and integrated MCC version

New features:

Bug fixes:

Scope: Synthesis backend, web version, and integrated MCC version

New features:

LOGIC-514, LOGIC-1537: BELS and .svg outputs
The backend synthesis process produces BELS output converted to a .svg image, which provides information regarding which BLEs are used in hardware. The images are available in the GUI and inside the ZIP archive.
LOGIC-1342: Verilog syntax errors are shown after failed synthesis
LOGIC-1533: Redefined LUT to Table to clarify that it does not necessarily map directly to a hardware LUT
LOGIC-1514: Updated start page
LOGIC-1452: New Verilog files now include a template
LOGIC-1290: Design sidebar is now context-sensitive

Bug fixes:

Scope: Synthesis backend, web version, and integrated MCC version

New features:

LOGIC-1071: Improved feedback to users from backend synthesis process

The CLB Synthesizer frontend GUI now includes a synthesis output tab, which gives more detailed information when backend synthesis fails.
LOGIC-1165: Prevent synthesis when design errors are present

The Synthesis button is now disabled when design errors are present and can be bypassed in the Preferences dialog for debugging purposes.
LOGIC-1099: Provide an easier access to library modules

The CLB library on GitHub is now accessible through the drawer menu in the Library section.

Bug fixes:

LOGIC-1096: Synthesis fails if an input port is connected directly to an output port

You can now use the CLB to route input ports directly to output ports.
LOGIC-1048: Unable to synthesize Verilog files containing multiple comments

The maximum file size limit has been increased in the backend server.

New and noteworthy: