2 Known Issues and Change Log

This section presents known issues, limitations and change logs for the Configurable Logic Block (CLB) Synthesizer.

The CLB Synthesizer toolchain is comprised of the following:
  • The synthesis engine (backend), hosted in the cloud
  • CLB Synthesizer GUI, hosted in the cloud at logic.microchip.com/clbsynthesizer/
  • CLB Synthesizer GUI integrated into MPLAB® Code Configurator (MCC), deployed via the MCC Content Manager

Releases are tracked using CalVer format. Components included in a release follow SemVer.

If available, include the ZIP archive from the synthesis process when contacting Microchip Support.

Known Issues and Limitations

  • LOGIC-34: Logic synthesis may fail when signals are optimized into constants

    A logic design can fail to synthesize if it has an output signal that becomes optimized into a constant. Examples include a Look-up Table (LUT) symbol populated with 0x0000 or 0xFFFF values, a signal combined with its inverse, or a constant 0 or 1 symbol.

    Workaround: Use the zero input port as a constant source

Simulator known issues:

  • LOGIC-2045: UART, PWM and SPI stimuli are missing start offset configuration (offset is always 0)
  • LOGIC-2055: It is not possible to use the simulator with designs that the built-in counter
  • LOGIC-2054: Internal nets and parameters are shown in the VCD viewer
  • LOGIC-1947: Changing the clock frequency causes the simulation cycles to change
  • LOGIC-2086: A zero port (constant) should not require inputs from a test bench

Release 26.5.1

Scope: Web frontend and integrated MCC version

Frontend Core version 2.2.0

New features:

  • LOGIC-2706: Added new variants for the PIC16F132xx device family
  • LOGIC-1371: Support for parametric Verilog modules
  • LOGIC-2762: Support for copy-and-paste of components between schematics
  • LOGIC-2871: Allow unconnected outputs in sheet modules
  • LOGIC-2747: Support triggering multiple peripherals from a single source
Bug fixes:
  • LOGIC-2384: Renaming the main schematic results in synthesis errors
  • LOGIC-2834: MCC/Melody removes dependent modules when synthesis fails
  • LOGIC-2998, LOGIC-2997, LOGIC-2996, and LOGIC-2898 Design checker improvements
  • LOGIC-2778, and LOGIC-2886: Large VCD files crash the frontend
  • LOGIC-2566: Simulation of T flip-flops fails
  • LOGIC-3012: The PIC18FQ35 SPI SDI1 and SCK1 lines into CLB are swapped

Release 26.3.1

Scope: Web frontend, synthesis backend, and integrated MCC version

Frontend Core version 2.1.0

New features:

  • Added a new device family, PIC18FQ35

Release 26.1.1

Scope: Synthesis backend

New features:
  • LOGIC-475: Added timing report output.

    After synthesis, a timing report provides an estimate of the maximum safe CLB clock frequency.

Release 25.12.1

Scope: Web frontend, synthesis backend, and integrated MCC version

New features:

  • Added a new device family: PIC16F13276
  • Enhancements to the I/O port properties panel to simplify signal selection

Release 25.6.1

Scope: Web frontend and integrated MCC version

New features:

  • LOGIC-2111: Markup output from the backend is displayed in the outputs section
  • LOGIC-2071: Remove the 'beta' tag from the Simulator feature
Bug fixes:
  • Numerous bug fixes in the Simulator

Release 25.3.1

Scope: Synthesis backend, web version, and integrated MCC version

New features:
  • LOGIC-1468: CLB Simulator (beta)
  • LOGIC-1692: New Help Center button was added
  • LOGIC-1920: Support for light and dark themes
Bug fixes:
  • LOGIC-1674: Consistent SVG outputs between pre- and post-routing
  • LOGIC-1913: Corrected stderr output

Release 24.12.1

Scope: Synthesis backend, web version, and integrated MCC version

New features:
  • LOGIC-514 and LOGIC-1537: BELS and .svg outputs

    The backend synthesis process produces BELS output that is converted to an .svg image, which provides information about which BLEs are used in hardware. The images are available in the GUI and within the ZIP archive.

  • LOGIC-1342: Verilog syntax errors are shown after a failed synthesis
  • LOGIC-1533: Redefined LUT as Table to clarify that it does not necessarily map directly to a hardware LUT
  • LOGIC-1514: Updated start page
  • LOGIC-1452: New Verilog files now include a template
  • LOGIC-1290: The design sidebar is now context-sensitive
Bug fixes:
  • LOGIC-1025: Port names no longer require pressing the Enter key
  • LOGIC-1343: stdout is now included in the ZIP archive
  • LOGIC-1526: Port rotation is working for submodules
  • LOGIC-1209: The top-level document is now correctly passed to YoSYS

Release 24.2.1

Scope: Synthesis backend, web version, and integrated MCC version

New features:

  • LOGIC-1071: Improved feedback to users from the backend synthesis process

    The CLB Synthesizer frontend GUI now includes a synthesis output tab, which provides more detailed information when backend synthesis fails.

  • LOGIC-1165: Prevent synthesis when design errors are present

    The Synthesis button is now disabled when design errors are present and can be bypassed in the Preferences dialog for debugging purposes.

  • LOGIC-1099: Provide easier access to library modules

    The CLB library on GitHub is now accessible through the drawer menu in the Library section.

Bug fixes:

  • LOGIC-1096: Synthesis fails if an input port is connected directly to an output port

    You can now use the CLB to route input ports directly to output ports.

  • LOGIC-1048: Unable to synthesize Verilog files containing multiple comments

    The maximum file size limit has been increased on the backend server.

Release 23.12.1

New and noteworthy:
  • Initial public release