3 Pin Allocation Tables

Table 3-1. 28-Pin Allocation Table
I/O⁽²⁾	28- Pin SPDIP, SSOP	28- Pin VQFN	A/D	Reference	Comp.	ZCD	Timers	16-Bit PWM/ CCP	CWG	DSM	CLB	CLC	SPI/ I²C	SRPORT	UART	IOC	Interrupt	Basic
RA0	2	27	ANA0	—	C1IN0- C2IN0-	—	—	—	—	—	CLBIN7⁽¹⁾	CLCIN0⁽¹⁾ CLCIN4⁽¹⁾	—	—	—	IOCA0	—	—
RA1	3	28	ANA1	—	C1IN1- C2IN1-	—	—	—	—	—	CLBCLK⁽¹⁾	CLCIN1⁽¹⁾ CLCIN5⁽¹⁾	—	—	—	IOCA1	—	—
RA2	4	1	ANA2	DAC1OUT1 V_REF- (DAC1) V_REF- (ADC)	C1IN0+ C2IN0+	—	—	—	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	2	ANA3	V_REF+ (DAC1) V_REF+ (ADC)	C1IN1+	—	—	—	—	MDCARL⁽¹⁾	—	—	—	—	—	IOCA3	—	—
RA4	6	3	ANA4	—	—	—	T0CKI⁽¹⁾	—	—	MDCARH⁽¹⁾	—	—	—	—	—	IOCA4	—	—
RA5	7	4	ANA5	—	—	—	—	—	—	MDSRC⁽¹⁾	—	—	SS1⁽¹⁾	—	—	IOCA5	—	—
RA6	10	7	ANA6	—	—	—	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT OSC2
RA7	9	6	ANA7	—	—	—	—	—	—	—	—	—	—	—	—	IOCA7	—	OSC1 CLKIN
RB0	21	18	ANB0	—	C2IN1+	ZCDIN	—	—	CWG1⁽¹⁾	—	—	—	—	PORTWIN1⁽¹⁾	—	IOCB0	INT0⁽¹⁾	—
RB1	22	19	ANB1	—	C1IN3- C2IN3-	—	—	—	—	—	—	—	—	PORTWCLK⁽¹⁾	—	IOCB1	INT1⁽¹⁾	—
RB2	23	20	ANB2	—	—	—	—	—	—	—	—	—	—	PORTWIN0⁽¹⁾	—	IOCB2	INT2⁽¹⁾	—
RB3	24	21	ANB3	—	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	—	—	IOCB3	—	—
RB4	25	22	ANB4 ADACT⁽¹⁾	—	—	—	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	26	23	ANB5	—	—	—	T1G⁽¹⁾ TUIN1⁽¹⁾	—	—	—	—	—	—	—	—	IOCB5	—	—
RB6	27	24	ANB6	—	—	—	—	—	—	—	—	CLCIN2⁽¹⁾ CLCIN6⁽¹⁾	—	—	CTS2⁽¹⁾	IOCB6	—	ICSPCLK
RB7	28	25	ANB7	DAC1OUT2	—	—	—	—	—	—	—	CLCIN3⁽¹⁾ CLCIN7⁽¹⁾	—	—	RX2⁽¹⁾	IOCB7	—	ICSPDAT
RC0	11	8	ANC0	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾ TUIN0⁽¹⁾	—	—	—	CLBIN0⁽¹⁾	—	—	—	—	IOCC0	—	SOSCO
RC1	12	9	ANC1	—	—	—	—	PWMIN1⁽¹⁾	—	—	CLBIN1⁽¹⁾	—	—	—	—	IOCC1	—	SOSCI
RC2	13	10	ANC2	—	—	—	—	PWMIN0⁽¹⁾ CCP1⁽¹⁾	—	—	CLBIN2⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3⁽⁶⁾	14	11	—	—	—	—	T2IN⁽¹⁾	PWM1ERS⁽¹⁾	—	—	CLBIN3⁽¹⁾	—	SCK1⁽¹⁾ SCL1^(3,4)	—	—	IOCC3	—	—
RC4⁽⁶⁾	15	12	—	—	—	—	—	—	—	—	CLBIN4⁽¹⁾	—	SDI1⁽¹⁾ SDA1^(3,4)	—	—	IOCC4	—	—
RC5⁽⁶⁾	16	13	—	—	—	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	—	CLBIN5⁽¹⁾	—	—	—	RX1⁽¹⁾	IOCC5	—	—
RC6⁽⁶⁾	17	14	—	—	—	—	—	—	—	—	CLBIN6⁽¹⁾	—	—	—	CTS1⁽¹⁾	IOCC6	—	—
RE3	1	26	—	—	—	—	—	—	—	—	—	—	—	—	—	IOCE3	—	V_PP/MCLR
V_DD⁽⁵⁾	20	17	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD⁽⁵⁾
V_DDIO2⁽⁵⁾	18	15	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DDIO2
V_SS	8, 19	5, 16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	C1OUT C2OUT	—	TMR0	PWM11 PWM12 PWM21 PWM22 CCP1	CWG1A CWG1B CWG1C CWG1D	DSM	CLBDEBUG0 CLBDEBUG1 CLBPPSOUT15 CLBPPSOUT14 CLBPPSOUT13 CLBPPSOUT12 CLBPPSOUT11 CLBPPSOUT10 CLBPPSOUT9 CLBPPSOUT8 CLBPPSOUT7 CLBPPSOUT6 CLBPPSOUT5 CLBPPSOUT4 CLBPPSOUT3 CLBPPSOUT2 CLBPPSOUT1 CLBPPSOUT0	CLC1OUT CLC2OUT CLC3OUT CLC4OUT CLC5OUT CLC6OUT CLC7OUT CLC8OUT	SS1 SCK1 SDO1 SDA1 SCL1	RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0	DTR1 RTS1 TX1 DTR2 RTS2 TX2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBUF/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. A 0.1 μF bypass capacitor to V_SS is required on the V_DD and V_DDIOx pins. MVIO pins, powered by V_DDIO2.

Table 3-2. 40/48-Pin Allocation Table
I/O⁽²⁾	40- Pin PDIP	40- Pin VQFN TQFP	48- Pin TQFP VQFN	A/D	Reference	Comparator	ZCD	Timers	16-Bit PWM/ CCP	CWG	DSM	CLB	CLC	SPI/ I²C	SRPORT	UART	IOC	Interrupt	Basic
RA0	2	17	21	ANA0	—	C1IN0- C2IN0-	—	—	—	—	—	CLBIN7⁽¹⁾	CLCIN0⁽¹⁾ CLCIN4⁽¹⁾	—	—	—	IOCA0	—	—
RA1	3	18	22	ANA1	—	C1IN1- C2IN1-	—	—	—	—	—	CLBCLK⁽¹⁾	CLCIN1⁽¹⁾ CLCIN5⁽¹⁾	—	—	—	IOCA1	—	—
RA2	4	19	23	ANA2	DAC1OUT1 V_REF- (DAC1) V_REF- (ADC)	C1IN0+ C2IN0+	—	—	—	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	20	24	ANA3	V_REF+ (DAC1) V_REF+ (ADC)	C1IN1+	—	—	—	—	MDCARL⁽¹⁾	—	—	—	—	—	IOCA3	—	—
RA4	6	21	25	ANA4	—	—	—	T0CKI⁽¹⁾	—	—	MDCARH⁽¹⁾	—	—	—	—	—	IOCA4	—	—
RA5	7	22	26	ANA5	—	—	—	—	—	—	MDSRC⁽¹⁾	—	—	SS1⁽¹⁾	—	—	IOCA5	—	—
RA6	14	29	33	ANA6	—	—	—	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT OSC2
RA7	13	28	32	ANA7	—	—	—	—	—	—	—	—	—	—	—	—	IOCA7	—	OSC1 CLKIN
RB0	33	8	8	ANB0	—	C2IN1+	ZCD1IN	—	—	CWG1⁽¹⁾	—	—	—	—	PORTWIN1⁽¹⁾	—	IOCB0	INT0⁽¹⁾	—
RB1	34	9	9	ANB1	—	C1IN3- C2IN3-	—	—	—	—	—	—	—	—	PORTWCLK⁽¹⁾	—	IOCB1	INT1⁽¹⁾	—
RB2	35	10	10	ANB2	—	—	—	—	—	—	—	—	—	—	PORTWIN0⁽¹⁾	—	IOCB2	INT2⁽¹⁾	—
RB3	36	11	11	ANB3	—	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	—	—	IOCB3	—	—
RB4	37	12	16	ANB4 ADACT⁽¹⁾	—	—	—	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	38	13	17	ANB5	—	—	—	T1G⁽¹⁾ TUIN1⁽¹⁾	—	—	—	—	—	—	—	—	IOCB5	—	—
RB6	39	14	18	ANB6	—	—	—	—	—	—	—	—	CLCIN2⁽¹⁾ CLCIN6⁽¹⁾	—	—	CTS2⁽¹⁾	IOCB6	—	ICSPCLK
RB7	40	15	19	ANB7	DAC1OUT2	—	—	—	—	—	—	—	CLCIN3⁽¹⁾ CLCIN7⁽¹⁾	—	—	RX2⁽¹⁾	IOCB7	—	ICSPDAT
RC0	15	30	34	ANC0	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾ TUIN0⁽¹⁾	—	—	—	CLBIN0⁽¹⁾	—	—	—	—	IOCC0	—	SOSCO
RC1	16	31	35	ANC1	—	—	—	—	PWMIN1⁽¹⁾	—	—	CLBIN1⁽¹⁾	—	—	—	—	IOCC1	—	SOSCI
RC2	17	32	40	ANC2	—	—	—	—	PWMIN0⁽¹⁾ CCP1⁽¹⁾	—	—	CLBIN2⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3⁽⁶⁾	18	33	41	—	—	—	—	T2IN⁽¹⁾	PWM1ERS⁽¹⁾	—	—	CLBIN3⁽¹⁾	—	SCK1⁽¹⁾ SCL1^(3,4)	—	—	IOCC3	—	—
RC4⁽⁶⁾	23	38	46	—	—	—	—	—	—	—	—	CLBIN4⁽¹⁾	—	SDI1⁽¹⁾ SDA1^(3,4)	—	—	IOCC4	—	—
RC5⁽⁶⁾	24	39	47	—	—	—	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	—	CLBIN5⁽¹⁾	—	—	—	RX1⁽¹⁾	IOCC5	—	—
RC6⁽⁶⁾	25	40	48	—	—	—	—	—	—	—	—	CLBIN6⁽¹⁾	—	—	—	CTS1⁽¹⁾	IOCC6	—	—
RD0⁽⁶⁾	19	34	42	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD1⁽⁶⁾	20	35	43	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD2⁽⁶⁾	21	36	44	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD3⁽⁶⁾	22	37	45	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD4⁽⁶⁾	27	2	2	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD5⁽⁶⁾	28	3	3	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD6⁽⁶⁾	29	4	4	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RD7⁽⁶⁾	30	5	5	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE0	8	23	27	ANE0	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE1	9	24	28	ANE1	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE2	10	25	29	ANE2	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RE3	1	16	20	—	—	—	—	—	—	—	—	—	—	—	—	—	IOCE3	—	V_PP/MCLR
RF0	—	—	36	ANF0	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF1	—	—	37	ANF1	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF2	—	—	38	ANF2	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF3	—	—	39	ANF3	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF4	—	—	12	ANF4	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF5	—	—	13	ANF5	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF6	—	—	14	ANF6	—	—	—	—	—	—	—	—	—	—	—	—	—	—
RF7	—	—	15	ANF7	—	—	—	—	—	—	—	—	—	—	—	—	—	—
V_DD⁽⁵⁾	11, 32	7, 26	7, 30	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD⁽⁵⁾
V_DDIO2⁽⁵⁾	26	1	1	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DDIO2
V_SS	12, 31	6, 27	6,31	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾				ADGRDA ADGRDB	—	C1OUT C2OUT	—	TMR0	PWM11 PWM12 PWM21 PWM22 CCP1	CWG1A CWG1B CWG1C CWG1D	DSM	CLBDEBUG0 CLBDEBUG1 CLBPPSOUT15 CLBPPSOUT14 CLBPPSOUT13 CLBPPSOUT12 CLBPPSOUT11 CLBPPSOUT10 CLBPPSOUT9 CLBPPSOUT8 CLBPPSOUT7 CLBPPSOUT6 CLBPPSOUT5 CLBPPSOUT4 CLBPPSOUT3 CLBPPSOUT2 CLBPPSOUT1 CLBPPSOUT0	CLC1OUT CLC2OUT CLC3OUT CLC4OUT CLC5OUT CLC6OUT CLC7OUT CLC8OUT	SS1 SCK1 SDO1 SDA1 SCL1	RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0	DTR1 RTS1 TX1 DTR2 RTS2 TX2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBUF/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. A 0.1 μF bypass capacitor to V_SS is required on all V_DD and V_DDIOx pins. MVIO pins, powered by V_DDIO2.