37.7 I/O Pins

Table 37-7. I/O Pin Specifications
SymbolDescriptionMin.Typ.✝ Max.UnitConditions
Input Low Voltage
VILI/O PORT:
  • with Schmitt Trigger buffer
——0.2×VDDV
  • with I2C levels
——0.3×VDDV
  • with SMBus 3.0 levels
——0.8V
RESET pin——0.2×VDDV
Input High Voltage
VIHI/O PORT:
  • with Schmitt Trigger buffer
0.8×VDD——V
  • with I2C levels
0.7×VDD——V
  • with SMBus 3.0 levels
1.35——V

0°C ≤ TA ≤ +125°C,

2.5V ≤ VDD ≤ 5.5V

1.45——V

0°C ≤ TA ≤ +125°C,

1.8V ≤ VDD ≤ 5.5V

RESET Pin0.8×VDD——V
Input Leakage Current(1)
IILI/O PORTS—±5±125nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

—±5±1000nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 125°C

RESET Pin(2)—±50±200nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

Pull-up Current
IPUR—150200μAVDD = 3.0V, VPIN = GND
Output Low Voltage
VOLStandard I/O ports——0.6VIOL = 10 mA, VDD = 3.0V
Output High Voltage
VOHStandard I/O portsVDD-0.7——VIOH = 6 mA, VDD = 3.0V
I/O Slew Rate
Rising slew rate—45—nsPORTCTRL.SRL = 0x01
Rising slew rate—22—nsPORTCTRL.SRL = 0x00
Falling slew rate—30—nsPORTCTRL.SRL = 0x01
Falling slew rate—16—nsPORTCTRL.SRL = 0x00
Pin Capacitance
CIOAll I/O pins—5—pF

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:
  1. The negative current is defined as the current sourced by the pin.
  2. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.