37.15 TWI

Figure 37-7. TWI - Timing Requirements
Table 37-21. TWI - Timing Specifications
SymbolDescriptionMin.Typ.✝Max.UnitCondition
VDDSupply voltage range1.8—5.5VfSCL ≤ 400 kHz
2.2—5.5fSCL ≤ 1 MHz
fSCLSCL clock frequency——1000kHzMax. frequency requires system clock at 10 MHz
VIHInput high voltage0.7×VDD——V
VILInput low voltage——0.3×VDDV
VHYSHysteresis of Schmitt Trigger inputs0.1×VDD0.4×VDDV
VOLOutput low voltage——0.2×VDDVIload = 20 mA, Fast mode+
——0.4VIload = 3 mA, Normal mode, VDD > 2V
——0.2×VDDIload = 3 mA, Normal mode, VDD ≤ 2V
IOLLow-level output current3——mAfSCL ≤ 400 kHz, VOL = 0.4V
20——fSCL ≤ 1 MHz, VOL = 0.4V
CB *Capacitive load for each bus line——400pFfSCL ≤ 100 kHz
——400fSCL ≤ 400 kHz
——550fSCL ≤ 1 MHz
tR *Rise time for both SDA and SCL——1000nsfSCL ≤ 100 kHz
20—300fSCL ≤ 400 kHz
——120fSCL ≤ 1 MHz
tOF *Output fall time from VIHmin to VILmax——250ns

fSCL ≤ 100 kHz

10 pF < CB < 400 pF

20×(VDD/5.5V)—250

fSCL ≤ 400 kHz

10 pF < CB < 400 pF

20×(VDD/5.5V)—120

fSCL ≤ 1 MHz

10 pF < CB < 400 pF

tSP *Spikes suppressed by the input filter0—50ns
ILInput current for each I/O pin——1µA0.1×VDD < VI < 0.9×VDD
CI *Capacitance for each I/O pin——10pF
RPValue of pull-up resistor(VDD-VOL(max)) /IOL—1000 ns/(0.8473×CB)ΩfSCL ≤ 100 kHz
——300 ns/(0.8473×CB)fSCL ≤ 400 kHz
——120 ns/(0.8473×CB)fSCL ≤ 1 MHz
tHD_STA *Hold time (repeated) Start condition4.0——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
TLOW *Low period of SCL Clock4.7——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.35——fSCL ≤ 1 MHz
THIGH *High period of SCL Clock4.0——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
tSU_STA *Setup time for a repeated Start condition4.7——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
tHD_DAT *Data hold time across all corners—0—nsSDAHOLD[1:0] = 0x0
300—900SDAHOLD[1:0] = 0x3
tSU_DATData setup time250——nsfSCL ≤ 100 kHz
100——fSCL ≤ 400 kHz
50——fSCL ≤ 1 MHz
tSU_STO *Setup time for Stop condition4——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
tBUF *Bus free time between a Stop and Start condition4.7——µsfSCL ≤ 100 kHz
1.3——fSCL ≤ 400 kHz

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.