31.3.3.3 Clock Generation

The ADC peripheral contains a prescaler that generates the ADC clock (CLK_ADC) from the peripheral clock (CLK_PER). The limitations of the ADC Conversion Timing Specifications in the ADC section of the Electrical Characteristics apply.

The prescaling is selected by writing to the Prescaler (PRESC) bit field in the Control C (ADCn.CTRLC) register. The prescaler begins counting when the ADC conversion starts and is reset for every new conversion. Refer to the figure ADC Prescaler.

When initiating a conversion by writing a ‘1’ to the Start Conversion (STCONV) bit in the ADCn.COMMAND register or from event, the conversion starts after one CLK_PER cycle. The prescaler is kept in Reset, as long as there is no ongoing conversion. This assures a fixed delay from the trigger to the actual start of a conversion of maximum two CLK_PER cycles.