3 Pin Allocation Tables

Table 3-1. 14-Pin Allocation Table
I/O	14-Pin SOIC/TSSOP	A/D	Reference	Operational Amplifier	Comparator	ZCD	Timers/SMT	16-Bit PWM/CCP	CWG	CLC	SPI	I²C	UART	DSM	IOC	Interrupts	Basic
RA0	13	ANA0	DAC1OUT1	OPA1IN3+ OPA1IN3-	C1IN0+	—	—	—	—	—	SS2⁽¹⁾	—	—	—	IOCA0	—	ICDDAT ICSPDAT
RA1	12	ANA1	VREF+ (ADC) VREF+ (DAC1) VREF+ (DAC2)	—	C1IN0- C2IN0-	—	—	—	—	—	—	—	—	MDSRC⁽¹⁾	IOCA1	—	ICDCLK ICSPCLK
RA2	11	ANA2	VREF- (ADC) VREF- (DAC1) VREF- (DAC2) DAC1OUT2	OPA1IN2+ OPA1IN2-	—	ZCDIN	T0CKI⁽¹⁾	—	CWGIN⁽¹⁾	—	—	—	—	—	IOCA2	INT0⁽¹⁾	—
RA3	4	—	—	—	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	ANA4	—	—	—	—	T1G⁽¹⁾	—	—	CLCIN3⁽¹⁾	—	—	RX3⁽¹⁾	—	IOCA4	INT1⁽¹⁾	CLKOUT SOSCO OSC2
RA5	2	ANA5	—	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾ SMT1WIN⁽¹⁾	PWM1ERS⁽¹⁾	—	—	—	—	CTS3⁽¹⁾	—	IOCA5	INT2⁽¹⁾	CLKIN SOSCI OSC1
RC0	10	ANC0	—	OPA1IN0+	C2IN0+	—	SMT1SIG⁽¹⁾	—	—	—	SCK1⁽¹⁾	SCL1^(3,4)	—	—	IOCC0	—	—
RC1	9	ANC1	—	OPA1IN0-	C1IN1- C2IN1-	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	CLCIN2⁽¹⁾	SDI1⁽¹⁾	SDA1^(3,4)	RX2⁽¹⁾	—	IOCC1	—	—
RC2	8	ANC2 ADACT⁽¹⁾	—	OPA1OUT	C1IN2- C2IN2-	—	—	PWM3ERS⁽¹⁾	—	—	—	—	CTS2⁽¹⁾	MDCARL⁽¹⁾	IOCC2	—	—
RC3	7	ANC3	—	OPA1IN1+ OPA1IN1-	C1IN3- C2IN3-	—	—	PWMIN2⁽¹⁾	—	CLCIN0⁽¹⁾	SS1⁽¹⁾	—	—	—	IOCC3	—	—
RC4	6	ANC4	—	—	—	—	T3G⁽¹⁾	—	—	CLCIN1⁽¹⁾	SCK2⁽¹⁾	—	CTS1⁽¹⁾	—	IOCC4	—	—
RC5	5	ANC5	—	—	—	—	T3CKI⁽¹⁾	CCP1IN⁽¹⁾ PWMIN1⁽¹⁾	—	—	SDI2⁽¹⁾		RX1⁽¹⁾	MDCARH⁽¹⁾	IOCC5	—	—
V_DD	1	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	14	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	ADCGRDA ADCGRDB	—	—	C1OUT C2OUT	—	TMR0	PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 CCP1	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SS1 SCK1 SD01 SS2 SCK2 SDO2	SDA1 SCL1	DTR1 RTS1 TX1 DTR2 RTS2 TX2 DTR3 RTS3 TX3	DSM1	—	—	—
Note: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. A 0.1 μF bypass capacitor to V_SS is required on the V_DD pin.

Table 3-2. 20-Pin Allocation Table
I/O	20-Pin PDIP/SOIC/SSOP	20-Pin VQFN	A/D	Reference	Operational Amplifier	Comparator	ZCD	Timers/SMT	16-Bit PWM/CCP	CWG	CLC	SPI	I²C	UART	DSM	IOC	Interrupts	Basic
RA0	19	16	ANA0	DAC1OUT1	OPA1IN3+ OPA1IN3-	C1IN0+	—	—	—	—	—	—	—	—	—	IOCA0	—	ICDDAT ICSPDAT
RA1	18	15	ANA1	VREF+ (ADC) VREF+ (DAC1) VREF+ (DAC2)	—	C1IN0- C2IN0-	—	—	—	—	—	SS2⁽¹⁾	—	—	MDSRC⁽¹⁾	IOCA1	—	ICDCLK ICSPCLK
RA2	17	14	ANA2	VREF- (ADC) VREF- (DAC1) VREF- (DAC2) DAC1OUT2	OPA1IN2+ OPA1IN2-	—	ZCDIN	—	—	CWGIN⁽¹⁾	CLCIN0⁽¹⁾	—	—	—	—	IOCA2	—	—
RA3	4	1	—	—	—	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	20	ANA4	—	—	—	—	T1G⁽¹⁾ SMT1SIG⁽¹⁾	—	—	—	—	—	—	—	IOCA4	—	CLKOUT SOSCO OSC2
RA5	2	19	ANA5	—	—	—	—	T2IN⁽¹⁾ SMT1WIN⁽¹⁾	PWM1ERS⁽¹⁾	—	—	—	—	—	—	IOCA5	—	CLKIN SOSCI OSC1
RB4	13	10	ANB4	—	OPA1IN0-	—	—	—	—	—	CLCIN2⁽¹⁾	SDI1⁽¹⁾	SDA1^(3,4)	—	—	IOCB4	—	—
RB5	12	9	ANB5	—	OPA1IN0+	—	—	—	—	—	CLCIN3⁽¹⁾	SDI2⁽¹⁾	—	RX1⁽¹⁾	—	IOCB5	—	—
RB6	11	8	ANB6	—	—	—	—	—	—	—	—	SCK1⁽¹⁾	SCL1^(3,4)	—	—	IOCB6	—	—
RB7	10	7	ANB7	—	—	—	—	—	—	—	—	SCK2⁽¹⁾	—	CTS1⁽¹⁾	—	IOCB7	—	—
RC0	16	13	ANC0	—	—	C2IN0+	—	—	—	—	—	—	—	—	—	IOCC0	INT0⁽¹⁾	—
RC1	15	12	ANC1	—	—	C1IN1- C2IN1-	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	—	—	—	RX2⁽¹⁾	—	IOCC1	INT1⁽¹⁾	—
RC2	14	11	ANC2 ADACT⁽¹⁾	—	OPA1OUT	C1IN2- C2IN2-	—	—	PWM3ERS⁽¹⁾	—	—	—	—	CTS2⁽¹⁾	MDCARL⁽¹⁾	IOCC2	INT2⁽¹⁾	—
RC3	7	4	ANC3	—	OPA1IN1+ OPA1IN1-	C1IN3- C2IN3-	—	—	PWMIN2⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	RX3⁽¹⁾	—	IOCC3	—	—
RC4	6	3	ANC4	—	—	—	—	T3G⁽¹⁾	—	—	—	—	—	—	—	IOCC4	—	—
RC5	5	2	ANC5	—	—	—	—	T3CKI⁽¹⁾ T0CKI⁽¹⁾	CCP1IN⁽¹⁾ PWMIN1⁽¹⁾	—	—	—	—	CTS3⁽¹⁾	MDCARH⁽¹⁾	IOCC5	—	—
RC6	8	5	ANC6	—	—	—	—	T1CKI⁽¹⁾	—	—	—	SS1⁽¹⁾	—	—	—	IOCC6	—	—
RC7	9	6	ANC7	—	—	—	—	—	—	—	—	—	—	—	—	IOCC7	—	—
V_DD	1	18	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	20	17	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADCGRDA ADCGRDB	—	—	C1OUT C2OUT	—	TMR0	PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 CCP1	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SS1 SCK1 SD01 SS2 SCK2 SDO2	SDA1 SCL1	DTR1 RTS1 TX1 DTR2 RTS2 TX2 DTR3 RTS3 TX3	DSM1	—	—	—
Note: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. A 0.1 μF bypass capacitor to V_SS is required on the V_DD pin.