1.5.3.1 How the Library Works

The PRIME User PIBs service library offers the PRIME Stack the necessary functions to handle the user PIBs, which include:
  • get user-defined parameters
  • set user-defined parameters
  • set callbacks

The PRIME Stack uses this interface to access the user PIBs when they are requested via MLME, Serial Profile or PRIME Profile by the user.

This library needs to be initialized. On PIC32CXMT devices it does not need to be maintained periodically; on the SAMD20 it must be maintained periodically through SRV_USER_PIB_Tasks (normally called from SYS_Tasks).

This library does not include storage. Users are responsible for adding and storing their own PIBs.

Currently, there are user PIBs related to the reset handling, which are populated by the Reset Handler Service. The available PIBs and where they are stored depend on the device.

PIC32CXMT

On PIC32CXMT devices, the reset-handling PIBs are stored in the GPBRs.

Table 1-21. PIC32CXMT Reset Handling User PIBs
PIBIDContents
PIB_USER_RESET_INFO0xF000number of resets + reset type
PIB_USER_PC0xF001PC
PIB_USER_LR0xF002LR
PIB_USER_PSR0xF003PSR
PIB_USER_HFSR0xF004HFSR
PIB_USER_CFSR0xF005CFSR
PIB_USER_R00xF006R0
PIB_USER_R10xF007R1
PIB_USER_R20xF008R2
PIB_USER_R30xF009R3
PIB_USER_R120xF00AR12

SAMD20

On the SAMD20, the user PIBs are stored in the emulated EEPROM. They comprise the reset-handling PIBs populated by the Reset Handler service and a bootloader-control PIB that requests the Bootloader Serial Recovery mode, as listed in the following table:

Table 1-22. User PIBs
PIBIDContents
PIB_USER_RESET_INFO0xF000number of resets + reset type
PIB_USER_PC0xF001PC
PIB_USER_LR0xF002LR
PIB_USER_PSR0xF003PSR
PIB_USER_R00xF006R0
PIB_USER_R10xF007R1
PIB_USER_R20xF008R2
PIB_USER_R30xF009R3
PIB_USER_R120xF00AR12
PIB_USER_BOOTLOADER_UART_MODE0xF010request the Bootloader Serial Recovery mode
Note: PIB_USER_HFSR (0xF004) and PIB_USER_CFSR (0xF005) are not used on the SAMD20, as these Arm Cortex-M4 fault status registers do not exist on the Arm Cortex-M0+ architecture.