3 Background

March tests are a family of memory tests used to assess specific fault models of variable/volatile memory, namely RAM or Static RAM (SRAM). The main idea is to “march” through the memory in ascending and descending order, cell by cell, and do write and read operations to sensitize and detect certain fault models. The design of a specific march element requires a systematic approach to mathematically prove that all the fault models in question are covered. The different march elements must be executed in a specific order, defined by the March algorithm, to ensure that all transitions are covered. The notation of March algorithms consists of prefixing each march element with an arrow and separating each march sequence with a semicolon. The arrows indicate an ascending (⇑ - start at lowest address in memory under test) or descending (⇓ - start at highest address in memory under test) order for the following march element. There is also the case where the address order does not matter (⇕). A march element consists of a sequence of write operations (w0 – write 0 or w1 – write 1) and read operations (r0 – read 0 or r1 – read 1). In the case of read operations, the cell is read and compared with the expected value (r0 expects 0 and r1 expects 1). All operations in a march element are performed on a single RAM cell (bit), before moving to the next cell in either ascending or descending order and the sequence is repeated. Once all cells in the memory under test have been tested with a march element, the next march element is executed.  

The most commonly used March algorithms are called March C- and March B. March C- is a slightly more efficient version of March C, where a redundant ‘r0’ operation is removed. In March notation, they are described as:  

March C-: {⇕(w0);⇑(r0,w1);⇑(r1,w0);⇓(r0,w1);⇓(r1,w0);⇕(r0)}  

March B: {⇕(w0);⇑(r0,w1,r1,w0,r0,w1);⇑(r1,w0,w1);⇓(r1,w0,w1,w0);⇓(r0,w1,w0)} Where, for example, ⇑(r0,w1,r1,w0,r0,w1) is March element number 1, or M1, of March B.

Both March B and March C- have been designed to cover the following fault models:

  • Stuck-at Faults (SAFs): The logic value of a cell (or line in the sense amplifier or driver) is always 0 or 1

  • Transition Faults (TFs): A cell fails to make a 0 to 1 transition or a 1 to 0 transition when it is written

  • Address Decoder Faults (AFs): Possible functional faults in the address decoders:

    • With a certain address, no cell will be accessed

    • Certain address accesses multiple cells

    • A certain cell is accessed with multiple addresses

    • Certain cells are accessed with their own and other addresses

  • Coupling Faults (CFs): Cases where a fault occurs in a cell because of coupling with other cells. The terminology distinguishes between aggressor cells (a-cell) and a victim cell (v-cell). That is, an operation performed on an a-cell can trigger a fault in the v-cell. There can be an exponential number of combinations in which a cell can be coupled with other cells. However, in the widely used coupling fault model, it is assumed that any two cells can be coupled together leading to irregular behavior in these two cells. This is called a two-cell coupling fault model. There are several categories of two-cell CFs and both March C- and March B cover the most common:

    • Inversion Coupling Faults (CFins): An upper (0 to 1) or lower (1 to 0) transition write operation in an a-cell causes an inversion (toggle) in the v-cell

    • Static/State Coupling Faults (CFsts): A given value 0 or 1 of the a-cell forces a certain value 0 or 1 in a v-cell

    • Idempotent Coupling Faults (CFid): An upper (0 to 1) or lower (1 to 0) transition write operation in an a-cell forces a certain value (0 or 1) in a v-cell

March B additionally covers some Linked Faults (LFs). LFs are the combinations of single and/or two-cell faults in which the faulty cell behaviour can be masked by faulty behavior due to another fault in the same cell. Linked Faults take place when more than one Fault Primitive (FP) is sensitized in a defective cell of a memory. Specifically, March B covers CFid-TF (CFid linked with TF) and CFid-CFid (CFid linked with CFid). Since March B covers more fault models than March C-, they differ in Test Length (TL), that is, the combined number of read and write instructions necessary to complete the test. The TL for March C- is 10*n while the TL for March B is 17*n, where n is the number of bits/cells in the memory under test.  

The March C algorithm is not implemented for this test, as although it has the same coverage as March C-, the execution time is longer. March B is also not implemented for this test, because it is more expensive for test length and code size. March B does not fully cover all LFs which are comparatively rare faults to occur.