20.3.3 PORTWCLK
Note: This register can
only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.
Name: | PORTWCLK |
Address: | 0x04A3 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CLK[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bits 4:0 – CLK[4:0] Signal Routing Port Clock Input Selection
CLK | Clock Input |
---|---|
11111
- 10110 | Reserved |
10101 | CLC4_OUT |
10100 | CLC3_OUT |
10011 | CLC2_OUT |
10010 | CLC1_OUT |
10001 | PWM2S1P2_OUT |
10000 | PWM2S1P1_OUT |
01111 | PWM1S1P2_OUT |
01110 | PWM1S1P1_OUT |
01101 | CCP2_OUT |
01100 | CCP1_OUT |
01011 | TU16B_OUT |
01010 | TU16A_OUT |
01001 | TMR4_OUT |
01000 | TMR2_OUT |
00111 | CLKREF_OUT |
00110 | EXTOSC |
00101 | SOSC |
00100 | MFINTOSC (32 kHz) |
00011 | MFINTOSC (500 kHz) |
00010 | LFINTOSC |
00001 | HFINTOSC |
00000 | FOSC |
Reset States: |
|