45.3.4 I/O Ports

Table 45-4. 
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.Device CharacteristicsMin.Typ.†Max.UnitsConditions
Input Low-Voltage
VILI/O PORT:
D300
  • with LVBUF (TTL-compatible)
——0.75V
D302
  • with Schmitt Trigger buffer
——0.2 VDDV2.0V ≤ VDD ≤ 5.5V
——0.2 VDDIOxV2.0V ≤ VDDIOx ≤ 5.5V
D303
  • with I2C levels
——0.3 VDDV2.0V ≤ VDD ≤ 5.5V
——0.3 VDDIOxV2.0V ≤ VDDIOx ≤ 5.5V
D304
  • with SMBus 2.0
——0.8V2.7V ≤ VDD ≤ 5.5V
D305
  • with SMBus 3.0
——0.8V
D306
  • with I3C Fast Schmitt Trigger buffer
——0.3 VDDIOxV1.62V ≤ VDDIOx ≤ 3.63V
  • with I3C Low-voltage buffer
——0.3 VDDIOxV0.95V ≤ VDDIOx ≤ 1.62V(3)
D307MCLR——0.2 VDDV
Input High-Voltage
VIHI/O PORT:
D320
  • with LVBUF (TTL-compatible)
1.5——V
D322
  • with Schmitt Trigger buffer
0.8 VDD——V2.0V ≤ VDD ≤ 5.5V
0.8 VDDIOx——V2.0V ≤ VDDIOx ≤ 5.5V
D323
  • with I2C levels
0.7 VDD——V
0.7 VDDIOx——V
D324
  • with SMBus 2.0
2.1——V2.7V ≤ VDD ≤ 5.5V; 2.7V ≤ VDDIOx ≤ 5.5V
D325
  • with SMBus 3.0
1.35——V
D326
  • with I3C Fast Schmitt Trigger buffer
0.7 VDDIOx——V1.62V ≤ VDDIOx ≤ 3.63V
  • with I3C Low-Voltage Buffer
0.7 VDDIOx—V0.95V ≤ VDDIOx ≤ 1.62V(3)
D327MCLR0.7 VDD——V
Input Hysteresis
VHYSI/O PORT:
D330
  • with I3C Fast Schmitt Trigger buffer
—0.1 VDDIOx—V1.62V ≤ VDDIOx ≤ 3.63V
D331
  • with I3C Low-voltage buffer
—0.1 VDDIOx—V0.95V ≤ VDDIOx ≤ 1.62V
Input Leakage Current(1)
D340IILI/O pins on VDD domain—±5±125nA

VSS ≤ VPIN ≤ VDD (VDD domain);

Pin at high-impedance, 85°C

D340A*I/O pins on MVIO domain—±5±125nA

VSS ≤ VPIN ≤ +6V (MVIO domain);

Pin at high-impedance, 85°C

D341I/O pins on VDD domain—±5±1000nA

VSS ≤ VPIN ≤ VDD (VDD domain);

Pin at high-impedance, 125°C

D341A*I/O pins on MVIO domain—±5±1000nA

VSS ≤ VPIN ≤ +6V (MVIO domain);

Pin at high-impedance, 125°C

D342MCLR(2)—±50±200nAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance, 85°C

Weak Pull-up Current
D350IPUR80140200μAVDD = 3.0V,

VPIN = VSS

Output Low-Voltage
VOLI/O PORT:
D360
  • with GPIO driver (all pins on VDD and MVIO domains)
——0.6VVPIN = 3.0V; IOL = 10 mA
D361
  • with I3C driver (I3C SDA pin only)
——0.18V0.95V < VDDIOx < 1.4V; IOL = 2 mA
——0.27V1.4V ≤ VDDIOx ≤ 3.63V; IOL = 3 mA
D362
  • with I2C pull-down driver (I3C SDA pin only)
———V0.95V < VDDIOx < 1.62V
Output High-Voltage
VOHI/O PORTS
D370
  • with GPIO driver (all pins on VDD and MVIO domains)
VDD - 0.7 ——VVVPIN = 3.0V; IOH = 6 mA
VDDIOx - 0.7——
D371
  • with I3C driver (I3C SDA pin only)
VDDIOx - 0.18——V0.95V < VDDIOx < 1.4V; IOH = -2 mA; Period of 50 µs
VDDIOx - 0.27——V1.4V ≤ VDDIOx ≤ 3.63V; IOH = -3 mA; Period of 50 µs
Load Capacitance
D380CIOAll I/O Pins (VDD and MVIO domains)—550pF
Input Capacitance
D390CIAll I/O Pins (VDD and MVIO domains)——5pF

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. Negative current is defined as current sourced by the pin.
  2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
  3. VDD > 2.4V is required for I3C Low-Voltage buffer operation in the range of 1.4V ≤ VDDIOx ≤ 1.62V