38.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics

Table 38-30. FDPLL96M Characteristics (Variant B and L With Silicon Revision E)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN	Input frequency		32	-	2000	KHz
f_OUT	Output frequency		48	-	96	MHz
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 48 MHz		500	733	μA
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 96 MHz		900	1235	μA
Jp	Period jitter	f_IN= 32 kHz, f_OUT= 48 MHz	-	2.1	3.2	%
		f_IN= 32 kHz, f_OUT= 96 MHz		4.0	6.9
		f_IN= 2 MHz, f_OUT= 48 MHz		2.2	3.6
		f_IN= 2 MHz, f_OUT= 96 MHz		4.7	8.2
t_LOCK	Lock Time	After startup, time to get lock signal. f_IN= 32 kHz, f_OUT= 96 MHz		1.2	2	ms
t_LOCK	Lock Time	f_IN= 2 MHz, f_OUT= 96 MHz		25	50	μs
Duty	Duty cycle		40	50	60	%

Table 38-31. FDPLL96M Characteristics⁽¹⁾ (Silicon Revision F and G)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN	Input frequency	-	32	-	2000	KHz
f_OUT	Output frequency	-	48	-	96	MHz
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 48 MHz	-	500	-	μA
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 96 MHz	-	900	-	μA
Jp	Period jitter	f_IN= 32 kHz, f_OUT= 48 MHz	-	2.1	3.0	%
		f_IN= 32 kHz, f_OUT= 96 MHz	-	3.8	9.2
		f_IN= 2 MHz, f_OUT= 48 MHz	-	2.2	3.2
		f_IN= 2 MHz, f_OUT= 96 MHz	-	4.4	10.0
t_LOCK	Lock Time	After startup, time to get lock signal. f_IN= 32 kHz, f_OUT= 96 MHz	-	1.2	2	ms
t_LOCK	Lock Time	f_IN= 2 MHz, f_OUT= 96 MHz	-	25	50	μs
Duty	Duty cycle	-	40	50	60	%

Note: 1. All values have been characterized with FILTSEL[1/0] as default value.

SAM D21/DA1 Family