39.6.3 Analog-to-Digital (ADC) characteristics

Table 39-13. Operating Conditions (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
VDDANA	Power Supply Voltage	T>105°C	3	-	3.6	V
RES	Resolution	-	8	-	12	bits
f_{CLK_ADC}	ADC Clock frequency	-	30	-	2100	kHz
	Sample rate⁽¹⁾	Single shot (with VDDANA > 3.0V)⁽⁴⁾	5	-	300	ksps
	Sample rate⁽¹⁾	Free running	5	-	350	ksps
	Sampling time⁽¹⁾	-	250	-	-	ns
	Sampling time with DAC as input⁽²⁾	-	3	-	-	µs
	Sampling time with Temp sens as input⁽²⁾	-	10	-	-	µs
	Sampling time with Bandgap as input⁽²⁾	-	10	-	-	µs
	Conversion time⁽¹⁾	1x Gain	6	-	-	cycles
V_REF	Voltage reference range (VREFA or VREFB)	-	1.0	-	V_DDANA-0.6	V
INT1V	Internal 1V reference ^(2,5)	-	-	1.0	-	V
INTVCC0	Internal ratiometric reference 0⁽²⁾	-	-	V_DDANA/1.48	-	V
INTVCC0 Voltage Error	Internal ratiometric reference 0⁽²⁾ error	2.0V < V_DDANA<3.63V	-1.0	-	+1.0	%
INTVCC1	Internal ratiometric reference 1⁽²⁾	V_DDANA>2.0V	-	V_DDANA/2	-	V
INTVCC1 Voltage Error	Internal ratiometric reference 1⁽²⁾ error	2.0V < V_DDANA<3.63V	-1.0	-	+1.0	%
	Conversion range⁽¹⁾	Differential mode	-V_REF/GAIN	-	+V_REF/GAIN	V
	Conversion range⁽¹⁾	Single-ended mode	0.0	-	+V_REF/GAIN	V
C_SAMPLE	Sampling capacitance⁽²⁾	-	-	3.5	-	pF
R_SAMPLE	Input channel source resistance⁽²⁾	-	-	-	3.5	kΩ
I_DD	DC supply current⁽¹⁾	f_{CLK_ADC} = 2.1MHz⁽³⁾	-	1.25	1.85	mA

Table 39-14. Operating Conditions (Device Variant B, C, D and L)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
VDDANA	Power Supply Voltage	T>105°C	3	-	3.6	V
RES	Resolution	-	8	-	12	bits
f_{CLK_ADC}	ADC Clock frequency	-	30	-	2100	kHz
	Conversion speed	-	10	-	1000	ksps
	Sample rate⁽¹⁾	Single shot	5	-	300	ksps
	Sample rate⁽¹⁾	Free running	5	-	350	ksps
	Sampling time⁽¹⁾	-	250	-	-	ns
	Sampling time with DAC as input⁽²⁾	-	3	-	-	µs
	Sampling time with Temp sens as input⁽²⁾	-	10	-	-	µs
	Sampling time with Bandgap as input⁽²⁾	-	10	-	-	µs
	Conversion time⁽¹⁾	1x Gain	6	-	-	cycles
V_REF	Voltage reference range (VREFA or VREFB)	-	1.0	-	V_DDANA-0.6	V
INTV1	Internal 1V reference ^(2,4)	-	-	1.0	-	V
INTVCC0	Internal ratiometric reference 0⁽²⁾	-	-	V_DDANA/1.48	-	V
INTVCC0 Voltage Error	Internal ratiometric reference 0⁽²⁾ error	2.0V < V_DDANA<3.63V	-1.0	-	+1.0	%
INTVCC1	Internal ratiometric reference 1⁽²⁾	V_DDANA>2.0V	-	V_DDANA/2	-	V
INTVCC1 Voltage Error	Internal ratiometric reference 1⁽²⁾ error	2.0V < V_DDANA<3.63V	-1.0	-	+1.0	%
	Conversion range⁽¹⁾	Differential mode	-V_REF/GAIN	-	+V_REF/GAIN	V
	Conversion range⁽¹⁾	Single-ended mode	0.0	-	+V_REF/GAIN	V
C_SAMPLE	Sampling capacitance⁽²⁾		-	3.5	-	pF
R_SAMPLE	Input channel source resistance⁽²⁾		-	-	3.5	kΩ
I_DD	DC supply current⁽¹⁾	f_{CLK_ADC} = 2.1MHz⁽³⁾	-	1.25	1.85	mA

Note:

These values are based on characterization, and are not covered by test limits in production.
These values are based on simulation, and are not covered by test limits in production or characterization.
In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC clock (conditions: 1X gain, 12-bit resolution, differential mode, free-running).
It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.

Table 39-15. Differential Mode (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number Of Bits	With gain compensation	-	10.5	10.9	bits
TUE	Total Unadjusted Error	1x Gain	1.5	4.3	17.0	LSB
INL	Integral Non Linearity	1x Gain	1.0	1.3	6.5	LSB
DNL	Differential Non Linearity	1x Gain	+/-0.3	+/-0.5	+/-0.95	LSB
GE	Gain Error	Ext. Ref 1x	-15.0	2.5	+20.0	mV
		V_REF=V_DDANA/1.48	-20.0	-1.5	+20.0	mV
		VREF = INT1V	-15.0	-5.0	+15.0	mV
	Gain Accuracy⁽⁵⁾	Ext. Ref. 0.5x	+/-0.1	+/-0.2	+/-0.45	%
	Gain Accuracy⁽⁵⁾	Ext. Ref. 2x to 16x	+/-0.1	+/-0.2	+/-2.0	%
OE	Offset Error	Ext. Ref. 1x	-10.0	-1.5	+10.0	mV
		V_REF=V_DDANA/1.48	-10.0	0.5	+15.0	mV
		VREF = INT1V	-10.0	3.0	+15.0	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_{CLK_ADC} = 2.1 MHz F_IN = 40 kHz A_IN = 95% FSR	64.2	70.0	78.9	dB
SINAD	Signal-to-Noise and Distortion		64.1	65.0	66	dB
SNR	Signal-to-Noise Ratio		64.3	65.5	66.0	dB
THD	Total Harmonic Distortion		-74.8	-64.0	-65.0	dB
	Noise RMS	T = 25°C	0.6	1.0	1.6	mV

Table 39-16. Differential Mode (Device Variant B, C, D and L)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number Of Bits	With gain compensation	-	10.5	10.8	bits
TUE	Total Unadjusted Error	1x Gain	1.5	2.7	14	LSB
INL	Integral Non Linearity	1x Gain	0.9	1.3	4	LSB
DNL	Differential Non Linearity	1x Gain	+/-0.3	+/-0.5	+/-0.95	LSB
GE	Gain Error	Ext. Ref 1x	-10.0	-1.3	+10	mV
		V_REF = V_DDANA/1.48	-25.0	-10.1	+10.0	mV
		VREF = INT1V	-25.0	+2	+10.0	mV
	Gain Accuracy⁽⁵⁾	Ext. Ref. 0.5x	+/-0.005	+/-0.05	+/-0.15	%
	Gain Accuracy⁽⁵⁾	Ext. Ref. 2x to 16x	+/-0.01	+/-0.03	+/-0.5	%
OE	Offset Error	Ext. Ref. 1x	-8.0	-1.0	+8.0	mV
		V_REF = V_DDANA/1.48	-8.0	-0.6	+8.0	mV
		VREF = INT1V	-6.0	-1.0	+8.0	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_{CLK_ADC} = 2.1 MHz F_IN = 40 kHz A_IN = 95% FSR	65.0	71.5	73.5	dB
SINAD	Signal-to-Noise and Distortion		58.0	65.0	67.0	dB
SNR	Signal-to-Noise Ratio		60.0	66	68.6	dB
THD	Total Harmonic Distortion		-73.0	-71.0	-67.0	dB
	Noise RMS	T = 25°C	0.6	1.0	1.6	mV

Note:

Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range.
Dynamic parameter numbers are based on characterization and not tested in production.
Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage):
- 1. If |VIN| > VREF/4
    - VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
    - VCM_IN > VREF/4 -0.05*VDDANA -0.1V
  2. If |VIN| < VREF/4
    - VCM_IN < 1.2*VDDANA - 0.75V
    - VCM_IN > 0.2*VDDANA - 0.1V
The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the V_DDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*V_ref/GAIN)

Table 39-17. Single-Ended Mode (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number of Bits	With gain compensation	-	9.5	9.8	Bits
TUE	Total Unadjusted Error	1x gain	-	10.5	14.0	LSB
INL	Integral Non-Linearity	1x gain	1.0	1.6	7.5	LSB
DNL	Differential Non-Linearity	1x gain	+/-0.5	+/-0.6	+/-0.95	LSB
GE	Gain Error	Ext. Ref. 1x	-10.0	0.7	+10.0	mV
	Gain Accuracy(4)	Ext. Ref. 0.5x	+/-0.1	+/-0.34	+/-0.4	%
	Gain Accuracy(4)	Ext. Ref. 2x to 16X	+/-0.01	+/-0.1	+/-0.15	%
OE	Offset Error	Ext. Ref. 1x	-5.0	1.5	+10.0	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_{CLK_ADC} = 2.1 MHz F_IN = 40 kHz A_IN = 95% FSR	63.1	65.0	66.5	dB
SINAD	Signal-to-Noise and Distortion		50.7	59.5	61.0	dB
SNR	Signal-to-Noise Ratio		49.9	60.0	64.0	dB
THD	Total Harmonic Distortion		-65.4	-63.0	-62.1	dB
	Noise RMS	T = 25°C	-	1.0	-	mV

Table 39-18. Single-Ended Mode (Device Variant B, C, D and L)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number of Bits	With gain compensation	-	9.7	10.1	Bits
TUE	Total Unadjusted Error	1x gain	-	7.9	40.0	LSB
INL	Integral Non-Linearity	1x gain	1.4	2.6	6.0	LSB
DNL	Differential Non-Linearity	1x gain	+/-0.6	+/-0.7	+/-0.95	LSB
GE	Gain Error	Ext. Ref. 1x	-5.0	0.6	+5.0	mV
	Gain Accuracy(4)	Ext. Ref. 0.5x	+/-0.1	+/-0.37	+/-0.55	%
	Gain Accuracy(4)	Ext. Ref. 2x to 16X	+/-0.01	+/-0.1	+/-0.2	%
OE	Offset Error	Ext. Ref. 1x	-5.0	0.6	+10.0	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_{CLK_ADC} = 2.1 MHz F_IN = 40 kHz A_IN = 95%FSR	63.0	68.0	68.7	dB
SINAD	Signal-to-Noise and Distortion		55.0	60.1	62.5	dB
SNR	Signal-to-Noise Ratio		54.0	61.0	64.0	dB
THD	Total Harmonic Distortion		-69.0	-68.0	-65.0	dB
	Noise RMS	T = 25°C	-	1.0	-	mV

Note:

Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range.
Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN:
- VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
- VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the V_DDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (V_ref/GAIN)

SAM D21/DA1 Family