37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics

Table 37-58. FDPLL96M Characteristics(1) (Device Variant A)
SymbolParameterConditionsMin.Typ.Max.Units
fINInput frequency32-2000KHz
fOUTOutput frequency48-96MHz
IFDPLL96MCurrent consumptionfIN= 32 kHz, fOUT= 48 MHz-500700μA
fIN= 32 kHz, fOUT= 96 MHz-9001200
JpPeriod jitterfIN= 32 kHz, fOUT= 48 MHz-1.52.0%
fIN= 32 kHz, fOUT= 96 MHz-3.010.0
fIN= 2 MHz, fOUT= 48 MHz-1.32.0
fIN= 2 MHz, fOUT= 96 MHz-3.07.0
tLOCKLock TimeAfter start-up, time to get lock signal.

fIN= 32 kHz, fOUT= 96 MHz

-1.32ms
fIN= 2 MHz, fOUT= 96 MHz-2550μs
DutyDuty cycle405060%
Table 37-59. FDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E)
SymbolParameterConditionsMin.Typ.Max.Units
fINInput frequency32-2000KHz
fOUTOutput frequency48-96MHz
IFDPLL96MCurrent consumptionfIN= 32 kHz, fOUT= 48 MHz-500700μA
fIN= 32 kHz, fOUT= 96 MHz-9001200
JpPeriod jitterfIN= 32 kHz, fOUT= 48 MHz-1.52.1%
fIN= 32 kHz, fOUT= 96 MHz-4.010.0
fIN= 2 MHz, fOUT= 48 MHz-1.62.2
fIN= 2 MHz, fOUT= 96 MHz-4.610.2
tLOCKLock TimeAfter start-up, time to get lock signal.

fIN= 32 kHz, fOUT= 96 MHz

-1.22ms
fIN= 2 MHz, fOUT= 96 MHz-2550μs
DutyDuty cycle405060%
Table 37-60. FDPLL96M Characteristics(1) (Silicon Revision F and G)
SymbolParameterConditionsMin.Typ.Max.Units
fINInput frequency32-2000KHz
fOUTOutput frequency48-96MHz
IFDPLL96MCurrent consumptionfIN= 32 kHz, fOUT= 48 MHz-500-μA
fIN= 32 kHz, fOUT= 96 MHz-900-
JpPeriod jitterfIN= 32 kHz, fOUT= 48 MHz-2.23.0%
fIN= 32 kHz, fOUT= 96 MHz-3.79.0
fIN= 2 MHz, fOUT= 48 MHz-2.23.0
fIN= 2 MHz, fOUT= 96 MHz-4.49.7
tLOCKLock TimeAfter start-up, time to get lock signal.

fIN= 32 kHz, fOUT= 96 MHz

-1.02ms
fIN= 2 MHz, fOUT= 96 MHz-2250μs
DutyDuty cycle405060%
Note: All values have been characterized with FILTSEL[1/0] as the default value.