33.6.10 Offset and Gain Correction

Inherent gain and offset errors affect the absolute accuracy of the ADC.

The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line at zero input voltage. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR). The offset correction value is subtracted from the converted data before writing to the Result register (RESULT).

The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line, after compensating for offset error. The gain error cancellation is handled by the Gain Correction register (GAINCORR).

To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register (CTRLB.CORREN) must be set.

Offset and gain error compensation results are both calculated according to:


Result = Conversion value + − OFFSETCORR ⋅ GAINCORR

The correction will introduce a latency of 13 CLK_ADC clock cycles. In Free-running mode this latency is introduced on the first conversion only because the duration is always less than the propagation delay. In Single Conversion mode this latency is introduced for each conversion.

Figure 33-8.  ADC Timing Correction Enabled