SAM D21/DA1 Family

37.13.3 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table 37-52. DFLL48M Characteristics - Open Loop Mode⁽¹⁾
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512	47	48	49	MHz
I_DFLL	Power consumption on V_DDIN	IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512	-	403	453	μA
t_STARTUP	Start-up time	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 f_OUTwithin 90 % of final value	-	8	9	μs

Note: 1. DFLL48M in Open loop after calibration at room temperature.

Table 37-53. DFLL48M Characteristics - Closed Loop Mode⁽¹⁾ (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Average Output frequency	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	47.963	47.972	47.981	MHz
f_REF	Reference frequency		0.732	32.768	33	kHz
Jitter	Cycle to Cycle jitter	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	-	-	0.42	ns
I_DFLL	Power consumption on V_DDIN	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	-	425	482	μA
t_LOCK	Lock time	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	100	200	500	μs

Table 37-54. DFLL48M Characteristics - Closed Loop Mode⁽¹⁾ (Device Variant B, C, D, and L)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Average Output frequency	f_REF = 32 .768kHz	47.963	47.972	47.981	MHz
f_REF	Reference frequency		0.732	32.768	33	kHz
Jitter	Cycle to Cycle jitter	f_REF = 32 .768kHz	-	-	0.42	ns
I_DFLL	Power consumption on V_DDIN	f_REF =32 .768kHz	-	403	453	μA
t_LOCK	Lock time	f_REF = 32 .768kHz DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	-	200	500	μs

To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy.

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