37.16.5 I²S Timing

Table 37-71. I2S Timing Characteristics and Requirements (Device Variant A)
Name	Description	Mode	VDD=1.8V			VDD=3.3V			Units
Name	Description	Mode	Min.	Typ.	Max	Min.	Typ.	Max.	Units
t_{M_MCKOR}	I2S MCK rise time⁽³⁾	Host mode / Capacitive load CL = 15 pF			9.2			4.7	ns
t_{M_MCKOF}	I2S MCK fall time⁽³⁾	Host mode / Capacitive load CL = 15 pF			11.5			5.3	ns
d_{M_MCKO}	I2S MCK duty cycle	Host mode	45.4		50	45.4		50	%
d_{M_MCKI}	I2S MCK duty cycle	Host mode, pin is input (1b)		50			50		%
t_{M_SCKOR}	I2S SCK rise time⁽³⁾	Host mode / Capacitive load CL = 15 pF			9			4.6	ns
t_{M_SCKOF}	I2S SCK fall time⁽³⁾	Host mode / Capacitive load CL = 15 pF			9.7			4.5	ns
d_{M_SCKO}	I2S SCK duty cycle	Host mode	45.6		50	45.6		50	%
f_{M_SCKO},1/t_{M_SCKO}	I2S SCK frequency	Host mode,Supposing external device response delay is 30ns			8			9.5	MHz
f_{S_SCKI},1/t_{S_SCKI}	I2S SCK frequency	Client mode,Supposing external device response delay is 30ns			14.4			14.8	MHz
d_{S_SCKO}	I2S SCK duty cycle	Client mode		50			50		%
t_{M_FSOV}	FS valid time	Host mode			4.1			4	ns
t_{M_FSOH}	FS hold time	Host mode	-0.9			-0.9			ns
t_{S_FSIS}	FS setup time	Client mode	2.3			1.5			ns
t_{S_FSIH}	FS hold time	Client mode	0			0			ns
t_{M_SDIS}	Data input setup time	Host mode	34.7			24.5			ns
t_{M_SDIH}	Data input hold time	Host mode	-8.2			-8.2			ns
t_{S_SDIS}	Data input setup time	Client mode	4.6			3.9			ns
t_{S_SDIH}	Data input hold time	Client mode	1.2			1.2			ns
t_{M_SDOV}	Data output valid time	Host transmitter			5.6			4.8	ns
t_{M_SDOH}	Data output hold time	Host transmitter	-0.5			-0.5			ns
t_{S_SDOV}	Data output valid time	Client transmitter			36.2			25.9	ns
t_{S_SDOH}	Data output hold time	Client transmitter	36			25.7			ns
t_PDM2LS	Data input setup time	Host mode PDM2 Left	34.7			24.5			ns
t_PDM2LH	Data input hold time	Host mode PDM2 Left	-8.2			-8.2			ns
t_PDM2RS	Data input setup time	Host mode PDM2 Right	30.5			20.9			ns
t_PDM2RH	Data input hold time	Host mode PDM2 Right	-6.7			-6.7			ns

Table 37-72. I2S Timing Characteristics and Requirements (Device Variant B, C and D)
Name	Description	Mode	VDD=1.8V			VDD=3.3V			Units
Name	Description	Mode	Min.	Typ.	Max.	Min.	Typ.	Max.	Units
t_{M_MCKOR}	I2S MCK rise time(3)	Host mode / Capacitive load CL = 15 pF			9.2			4.7	ns
t_{M_MCKOF}	I2S MCK fall time(3)	Host mode / Capacitive load CL = 15 pF			11.6			5.4	ns
d_{M_MCKO}	I2S MCK duty cycle	Host mode	47.1		50	47.3		50	%
d_{M_MCKI}	I2S MCK duty cycle	Host mode, pin is input (1b)		50			50		%
t_{M_SCKOR}	I2S SCK rise time(3)	Host mode / Capacitive load CL = 15 pF			9			4.6	ns
t_{M_SCKOF}	I2S SCK fall time(3)	Host mode / Capacitive load CL = 15 pF			9.7			4.6	ns
d_{M_SCKO}	I2S SCK duty cycle	Host mode	47		50	47.2		50	%
f_{M_SCKO}, 1/t_{M_SCKO}	I2S SCK frequency	Host mode, Supposing external device response delay is 30ns			7.8			9.2	MHz
f_{S_SCKI}, 1/t_{S_SCKI}	I2S SCK frequency	Client mode, Supposing external device response delay is 30ns			12.8			13	MHz
d_{S_SCKO}	I2S SCK duty cycle	Client mode		50			50		%
t_{M_FSOV}	FS valid time	Host mode			2.4			1.9	ns
t_{M_FSOH}	FS hold time	Host mode	-0.1			-0.1			ns
t_{S_FSIS}	FS setup time	Client mode	6			5.3			ns
t_{S_FSIH}	FS hold time	Client mode	0			0			ns
t_{M_SDIS}	Data input setup time	Host mode	36			25.9			ns
t_{M_SDIH}	Data input hold time	Host mode	-8.2			-8.2			ns
t_{S_SDIS}	Data input setup time	Client mode	9.1			8.3			ns
t_{S_SDIH}	Data input hold time	Client mode	3.8			3.7			ns
t_{M_SDOV}	Data output valid time	Host transmitter			2.5			1.9	ns
t_{M_SDOH}	Data output hold time	Host transmitter	-0.1			-0.1			ns
t_{S_SDOV}	Data output valid time	Client transmitter			29.8			19.7	ns
t_{S_SDOH}	Data output hold time	Client transmitter	29.1			18.9			ns
t_PDM2LS	Data input setup time	Host mode PDM2 Left	35.5			25.3			ns
t_PDM2LH	Data input hold time	Host mode PDM2 Left	-8.2			-8.2			ns
t_PDM2RS	Data input setup time	Host mode PDM2 Right	30.6			21.1			ns
t_PDM2RH	Data input hold time	Host mode PDM2 Right	-7			-7			ns

Note:

All timing characteristics given for 15pF capacitive load.
These values are based on simulations and not covered by test limits in production.
See I/O Pin Characteristics

SAM D21/DA1 Family

37.16.5 I2S Timing

37.16.5 I²S Timing