40.9.3 Analog-to-Digital (ADC) Characteristics

Table 40-24. Operating Conditions (Device Variant A)
Symbol	Parameters	Conditions	Min	Typ	Max	Unit
V_DDANA	Power supply voltage		2.7	-	3.6	V
Res	Resolution		8	-	12	bits
f_{CLK_ADC}	ADC Clock frequency		30	-	2100	kHz
	Sampling rate⁽²⁾	Single shot (with V_DDANA > 3.0V)⁽⁴⁾	5	-	300	ksps
	Sampling rate⁽²⁾	Free running	5	-	350	ksps
	Sampling time⁽²⁾		250	-	-	ns
	Sampling time with DAC as input⁽²⁾		3	-	-	µs
	Sampling time with Temp sens as input⁽²⁾		10	-	-	µs
	Sampling time with Bandgap as input⁽²⁾		10	-	-	µs
	Conversion time⁽²⁾	1x Gain	6	-	-	Cycles
V_REF	Voltage reference range (VREFA or VREFB)		1	-	V_DDANA-0.6	V
INT1V	Internal 1V reference ^(2,5)		-	1	-	V
INTVCC0	Internal ratiometric reference 0⁽²⁾		-	V_DDANA/1.48	-	V
INTVCC0 Voltage Error	Internal ratiometric reference 0⁽²⁾ error	2.0V < V_DDANA<3.63V	-1	-	1	%
INTVCC1	Internal ratiometric reference 1⁽²⁾	V_DDANA>2.0V	-	V_DDANA/2	-	V
INTVCC1 Voltage Error	Internal ratiometric reference 1⁽²⁾ error	2.0V < V_DDANA<3.63V	-1	-	1	%
	Conversion range⁽²⁾	Differential mode	-V_REF/GAIN	-	+V_REF/GAIN	V
		Single-ended mode	0	-	+V_REF/GAIN	V
C_SAMPLE	Sampling capacitance⁽²⁾		-	3.5	-	pF
R_SAMPLE	Input channel source resistance⁽²⁾		-	-	3.5	kohms
I_DD	DC supply current⁽¹⁾	f_{CLK_ADC} = 2.1MHzI⁽³⁾	-	1.25	3.9	mA

Table 40-25. Operating Conditions (Device Variant B and D)
Symbol	Parameters	Conditions	Min	Typ	Max	Unit
V_DDANA	Power supply voltage		2.7	-	3.6	V
Res	Resolution		8	-	12	bits
f_{CLK_ADC}	ADC Clock frequency		30	-	2100	kHz
	Sampling rate⁽¹⁾	Single shot	5	-	300	ksps
	Sampling rate⁽¹⁾	Free running	5	-	350	ksps
	Sampling time⁽¹⁾		250	-	-	ns
	Sampling time with DAC as input⁽²⁾		3	-	-	µs
	Sampling time with Temp sens as input⁽²⁾		10	-	-	µs
	Sampling time with Bandgap as input⁽²⁾		10	-	-	µs
	Conversion time⁽¹⁾	1x Gain	6	-	-	Cycles
V_REF	Voltage reference range (VREFA or VREFB)		1	-	V_DDANA-0.6	V
INT1V	Internal 1V reference^(2,5)		-	1	-	V
INTVCC0	Internal ratiometric reference 0⁽²⁾		-	V_DDANA/1.48	-	V
INTVCC0 Voltage Error	Internal ratiometric reference 0⁽²⁾ error	2.0V < V_DDANA<3.63V	-1	-	1	%
INTVCC1	Internal ratiometric reference 1⁽²⁾	V_DDANA>2.0V	-	V_DDANA/2	-	V
INTVCC1 Voltage Error	Internal ratiometric reference 1⁽²⁾ error	2.0V < V_DDANA<3.63V	-1	-	1	%
	Conversion range⁽¹⁾	Differential mode	-V_REF/GAIN	-	+V_REF/GAIN	V
		Single-ended mode	0	-	+V_REF/GAIN	V
C_SAMPLE	Sampling capacitance⁽²⁾		-	3.5	-	pF
R_SAMPLE	Input channel source resistance⁽²⁾		-	-	3.5	kohms
I_DD	DC supply current⁽¹⁾	f_{CLK_ADC} = 2.1MHzI⁽³⁾	-	1.25	4.7	mA

Note:

These values are based on characterization. These values are not covered by test limits in production.
These values are based on simulation. These values are not covered by test limits in production or characterization.
In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC clock.
All single-shot measurements are performed with V_DDANA > 3.0V (cf. ADC errata).
It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.

Table 40-26. Differential Mode : FCLK_ADC = 2.1MHz (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number Of Bits	With gain compensation	-	9.9	10.1	bits
TUE	Total Unadjusted Error	1x Gain	2.9	4.6	12.4	LSB
INL	Integral Non Linearity	1x Gain	1.4	2.2	6.5	LSB
DNL	Differential Non Linearity	1x Gain	+/-0.3	+/-0.5	+/-0.95	LSB
GE	Gain Error	Ext. Ref 1x	-24	-2.5	24	mV
		V_REF=V_DDANA/1.48	-25	-1.5	25	mV
		VREF = INT1V	-13	-5	+13	mV
	Gain Accuracy⁽⁵⁾	Ext. Ref. 0.5x	+/-0.1	+/-0.2	+/-0.45	%
	Gain Accuracy⁽⁵⁾	Ext. Ref. 2x to 16x	+/-0.1	+/-0.2	+/-2	%
OE	Offset Error	Ext. Ref. 1x	-10	-2	10	mV
		V_REF=V_DDANA/1.48	-10	0.5	15	mV
		VREF = INT1V	-10	3	15	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_IN = 40kHz A_IN = 95%FSR	64.2	70	78.9	dB
SINAD	Signal-to-Noise and Distortion		60.4	61.1	62.7	dB
SNR	Signal-to-Noise Ratio		63.4	64.4	66	dB
THD	Total Harmonic Distortion		-65.0	-64.0	-62.6	dB
	Noise RMS	T=25°C	0.6	1	2.5	mV

Table 40-27. Differential Mode : FCLK_ADC = 2.1MHz (Device Variant B and D)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number Of Bits	With gain compensation	-	10.5	10.8	bits
TUE	Total Unadjusted Error	1x Gain	1.5	2.9	14	LSB
INL	Integral Non Linearity	1x Gain	0.9	1.3	4	LSB
DNL	Differential Non Linearity	1x Gain	+/-0.3	+/-0.5	+/-0.95	LSB
GE	Gain Error	Ext. Ref 1x	-15	-2.4	15	mV
		V_REF=V_DDANA/1.48	-56	-14	56	mV
		VREF = INT1V	-36	-7	36	mV
	Gain Accuracy⁽⁵⁾	Ext. Ref. 0.5x	-	+/-0.1	+/-0.7	%
	Gain Accuracy⁽⁵⁾	Ext. Ref. 2x to 16x	-	+/-0.04	+/-0.5	%
OE	Offset Error	Ext. Ref. 1x	-8	1.7	8	mV
		V_REF=V_DDANA/1.48	-8	1.6	9	mV
		VREF = INT1V	-6	1.8	8	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_IN = 40kHz A_IN = 95%FSR	63.7	69.5	71.5	dB
SINAD	Signal-to-Noise and Distortion		56.8	63.7	65.6	dB
SNR	Signal-to-Noise Ratio		58.8	64.6	66.6	dB
THD	Total Harmonic Distortion		-71.5	-69.5	-65.6	dB
	Noise RMS	T=25°C	-	1	2.5	mV

Note:

Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range.
Dynamic parameter numbers are based on characterization and not tested in production.
Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage):
- 1. If |VIN| > VREF/4
    - VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
    - VCM_IN > VREF/4 -0.05*VDDANA -0.1V
  2. If |VIN| < VREF/4
    - VCM_IN < 1.2*VDDANA - 0.75V
    - VCM_IN > 0.2*VDDANA - 0.1V
The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the V_DDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the V_DDANA power supply.
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*V_REF/GAIN).

Table 40-28. Single Ended Mode FCLK_ADC = 2.1MHz (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number of Bits	With gain compensation	-	9.5	9.8	Bits
TUE	Total Unadjusted Error	1x gain	-	8.4	14.7	LSB
INL	Integral Non-Linearity	1x gain	1.6	2.6	7.5	LSB
DNL	Differential Non-Linearity	1x gain	+/-0.5	+/-0.6	+/-0.95	LSB
GE	Gain Error	Ext. Ref. 1x	-10	0.7	10	mV
	Gain Accuracy⁽⁴⁾	Ext. Ref. 0.5x	+/-0.1	+/-0.3	+/-0.4	%
	Gain Accuracy⁽⁴⁾	Ext. Ref. 2x to 16X	+/-0.01	+/-0.1	+/-0,65	%
OE	Offset Error	Ext. Ref. 1x	-17	0.2	1	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_IN = 40kHz A_IN = 95%FSR	63	65	66.5	dB
SINAD	Signal-to-Noise and Distortion		50.7	59.5	61	dB
SNR	Signal-to-Noise Ratio		57.6	60	64	dB
THD	Total Harmonic Distortion		-64.4	-63	-57.9	dB
-	Noise RMS	T = 25°C	-	1	-	mV

Table 40-29. Single Ended Mode FCLK_ADC = 2.1MHz (Device Variant B and D)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number of Bits	With gain compensation	-	9.5	10.1	Bits
TUE	Total Unadjusted Error	1x gain	-	7.8	40	LSB
INL	Integral Non-Linearity	1x gain	1.4	2.6	6	LSB
DNL	Differential Non-Linearity	1x gain	+/-0.6	+/-0.7	+/-0.95	LSB
GE	Gain Error	Ext. Ref. 1x	-6.6	0.6	6.6	mV
	Gain Accuracy⁽⁴⁾	Ext. Ref. 0.5x	+/-0.1	+/-0.37	+/-0.55	%
	Gain Accuracy⁽⁴⁾	Ext. Ref. 2x to 16X	+/-0.01	+/-0.1	+/-0.3	%
OE	Offset Error	Ext. Ref. 1x	-5	3.2	12	mV
SFDR	Spurious Free Dynamic Range	1x Gain F_IN = 40kHz A_IN = 95%FSR	61.7	66.6	66.6	dB
SINAD	Signal-to-Noise and Distortion		53.9	58.8	60.7	dB
SNR	Signal-to-Noise Ratio		52.9	59.7	62.7	dB
THD	Total Harmonic Distortion		-67.6	-66.6	-63.7	dB
-	Noise RMS	T = 25°C	-	1	6	mV

Note:

Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range.
Respect the input common mode voltage through the following equations (where V_{CM_IN} is the Input channel common mode voltage) for all V_IN:
- VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
- VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the V_DDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the V_DDANA power supply.
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (V_REF/GAIN).

SAM D21/DA1 Family