11.4.2 Configuration

Table 11-4. Bus Matrix Hosts

Bus Matrix Hosts	Host ID
CM0+ - Cortex M0+ Processor	0
DSU - Device Service Unit	1
DMAC - Direct Memory Access Controller - Data Access	2

Table 11-5. Bus Matrix Clients

Bus Matrix Clients	Client ID
Internal Flash Memory	0
AHB-APB Bridge A	1
AHB-APB Bridge B	2
AHB-APB Bridge C	3
SRAM Port 4 - CM0+ Access	4
SRAM Port 5 - DMAC Data Access	5
SRAM Port 6 - DSU Access	6

Table 11-6. SRAM Port Connection

SRAM Port Connection	Port ID	Connection Type
MTB - Micro Trace Buffer	0	Direct
USB - Universal Serial Bus	1	Direct
DMAC - Direct Memory Access Controller - Write-Back Access	2	Direct
DMAC - Direct Memory Access Controller - Fetch Access	3	Direct
CM0+ - Cortex M0+ Processor	4	Bus Matrix
DMAC - Direct Memory Access Controller - Data Access	5	Bus Matrix
DSU - Device Service Unit	6	Bus Matrix