41.15.4 SWD Timing

Figure 41-23. SWD Interface Signals
Table 41-57. SWD Timings(1)
SymbolParameterConditionsMin.Max.Units
ThighSWDCLK High periodVVDDIO from 3.0 V to 3.6 V, maximum external capacitor = 40 pF10500000ns
TlowSWDCLK Low period10500000
TosSWDIO output skew to falling edge SWDCLK-55
TisInput Setup time required between SWDIO4-
TihInput Hold time required between SWDIO and rising edge SWDCLK1-

Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization.