SAM D21/DA1 Family

41.15.4 SWD Timing

Table 41-57. SWD Timings⁽¹⁾
Symbol	Parameter	Conditions	Min.	Max.	Units
T_high	SWDCLK High period	V_VDDIOfrom 3.0 V to 3.6 V, maximum external capacitor = 40 pF	10	500000	ns
T_low	SWDCLK Low period		10	500000
T_os	SWDIO output skew to falling edge SWDCLK		-5	5
T_is	Input Setup time required between SWDIO		4	-
T_ih	Input Hold time required between SWDIO and rising edge SWDCLK		1	-

Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization.

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