11.4.3 SRAM Quality of Service
To ensure that hosts with latency requirements get sufficient priority when accessing RAM, the different hosts can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each host accessing the RAM. For any access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in the following table.
| Value | Name | Description |
|---|---|---|
00 | DISABLE | Background (no sensitive operation) |
01 | LOW | Sensitive Bandwidth |
10 | MEDIUM | Sensitive Latency |
11 | HIGH | Critical Latency |
If a host is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access.
The priority order for concurrent accesses are decided by two factors. First the QoS level for the host and then a static priority given by the SRAM Port Connection table where the lowest port ID has the highest static priority.
The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.
The CPU QoS level can be written/read at address 0x41007120, bits [1:0]. Its reset value is 0x2.
Refer to different host QOSCTRL registers for configuring QoS for the other hosts (USB, DMAC).