41.10.4 Analog-to-Digital Characteristics (ADC)
| Parameter | Conditions | Symbol | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Resolution | - | RES | 8 | - | 12 | bits |
| ADC Clock frequency | - | fCLK_ADC | 30 | - | 2100 | kHz |
| Sample rate (1) | Single shot | - | 5 | - | 300 | ksps |
| Free running | 5 | - | 350 | ksps | ||
| Sampling time (1) | - | - | 250 | - | - | ns |
| Sampling time with DAC as input(2) | - | - | 3 | - | - | µs |
| Sampling time with Temp sens as input(2) | - | - | 10 | - | - | µs |
| Sampling time with Bandgap as input(2) | - | - | 10 | - | - | µs |
| Conversion time(1) | 1x Gain | - | 6 | - | - | cycles |
| Voltage reference
range (VREFA or VREFB) | - | VREF | 1.0 | - | VDDANA – 0.6 | V |
| Internal 1V reference(2, 4) | - | INT1V | - | 1 | - | V |
| Internal ratiometric reference 0(2) | - | INTVCC0 | - | VDDANA/1.48 | - | V |
| Internal ratiometric reference 0(2) error | 2.0V < VDDANA<3.63V | INTVCC0
Voltage Error | -1 | - | 1 | % |
| Internal ratiometric reference 1(2) | VDDANA > 2.0V | INTVCC1 | - | VDDANA/2 | - | V |
| Internal ratiometric reference 1(2) error | 2.0V < VDDANA < 3.63V | INTVCC1
Voltage Error | –1 | - | 1 | % |
| Conversion range(1) | Differential mode | –VREF/GAIN | - | +VREF/GAIN | V | |
| Single-ended mode | 0 | - | +VREF/GAIN | V | ||
| Sampling capacitance (2) | - | CSAMPLE | - | 3.5 | - | pF |
| Input channel source resistance(2) | - | RSAMPLE | - | - | 3.5 | kΩ |
| DC supply current(1) | fCLK_ADC = 2.1 MHz(3) | IDD | - | 2.9 | 4.1 | mA |
Note:
- These values are based on characterization, and are not covered by test limits in production.
- These values are based on simulation, and are not covered by test limits in production or characterization.
- In this condition and for a sample rate of 350 ksps, 1 conversion at gain 1x takes 6 clock cycles of the ADC clock.
- It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
| Parameter | Conditions | Symbol | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Effective Number Of Bits | With gain compensation | ENOB | - | 10.4 | 10.8 | bits |
| Total Unadjusted Error | 1x Gain | TUE | 1.2 | 7.0 | 38.0 | LSB |
| Integral Non-linearity | 1x Gain | INL | 0.7 | 1.30 | 5.6 | LSB |
| Differential Non-linearity | 1x Gain | DNL | - | ±0.7 | ±0.95 | LSB |
| Gain Error | Ext. Ref 1x | GE | - | ±3 | ±13 | mV |
| VREF = VDDANA/1.48 | - | ±11 | ±55 | mV | ||
| VREF = INT1V | - | ±2 | ±35 | mV | ||
| Gain Accuracy(5) | Ext. Ref. 0.5x | - | ±0.1 | ±0.8 | % | |
| Ext. Ref. 2x to 16x | - | ±0.6 | ±0.9 | % | ||
| Offset Error | Ext. Ref. 1x | OE | - | ±2 | ±35 | mV |
| VREF=VDDANA/1.48 | - | ±3 | ±40 | mV | ||
| VREF = INT1V | - | ±3 | ±50 | mV | ||
| Spurious Free Dynamic Range | 1x Gain FCLK_ADC = 2.1 MHz FIN = 40 kHz AIN = 95% FSR | SFDR | 65 | 71.5 | 76 | dB |
| Signal-to-Noise and Distortion | SINAD | 58 | 65 | 67 | dB | |
| Signal-to-Noise Ratio | SNR | 60 | 66 | 68.6 | dB | |
| Total Harmonic Distortion | THD | –75 | –71 | –67 | dB | |
| Noise RMS | T = 25°C | 0.6 | 1 | 2.5 | mV |
Note:
- Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range.
- Dynamic parameter numbers are based on characterization and not tested in production.
- Respect the Input Common mode voltage through the following
equations (where, VCM_IN is the Input Channel Common mode voltage):
If |VIN| > VREF/4
VCM_IN < 0.95 × VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 -0.05 × VDDANA – 0.1V
If |VIN| < VREF/4
VCM_IN < 1.2 × VDDANA – 0.75V
VCM_IN > 0.2 × VDDANA – 0.1V
- The ADC channels on the pins, PA08, PA09, PA10, PA11, are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
- The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V × 100) / (2 × Vref/GAIN)
| Parameter | Conditions | Symbol | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Effective Number of Bits | With gain compensation | ENOB | - | 9.6 | 10.1 | Bits |
| Total Unadjusted Error | 1x gain | TUE | 3 | 11 | 74 | LSB |
| Integral Non-linearity | 1x gain | INL | 1 | 4 | 11 | LSB |
| Differential Non-linearity | 1x gain | DNL | - | ±0.5 | ±0.95 | LSB |
| Gain Error | Ext. Ref. 1x | GE | - | ±0.9 | ±10 | mV |
| Gain Accuracy(4) | Ext. Ref. 0.5x | - | ±0.2 | ±0.5 | % | |
| Ext. Ref. 2x to 16X | - | ±0.15 | ±0.3 | % | ||
| Offset Error | Ext. Ref. 1x | OE | - | ±3 | ±40 | mV |
| Spurious Free Dynamic Range | 1x Gain FCLK_ADC = 2.1 MHz FIN = 40 kHz AIN = 95%FSR | SFDR | 63 | 68 | 70.1 | dB |
| Signal-to-Noise and Distortion | SINAD | 55 | 60.1 | 62.5 | dB | |
| Signal-to-Noise Ratio | SNR | 54 | 61 | 64 | dB | |
| Total Harmonic Distortion | THD | –70 | –68 | –65 | dB | |
| Noise RMS | T = 25°C | - | 1 | 5 | mV |
Note:
- Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range.
- Respect the input common mode voltage through the following
equations, where VCM_IN is the Input Channel Common mode voltage for all VIN:
VCM_IN < 0.7 × VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 – 0.3 × VDDANA – 0.1V
- The ADC channels on the pins, PA08, PA09, PA10, PA11, are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
- The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V × 100) / (Vref/GAIN).