40.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics

Table 40-58. FDPLL96M Characteristics⁽¹⁾ (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN	Input frequency	-	32	-	2000	kHz
f_OUT	Output frequency	-	48	-	64	MHz
I_FDPLL96M	Current consumption	fIN= 32 kHz, fOUT= 48 MHz	-	500	700	µA
I_FDPLL96M	Current consumption	fIN= 32 kHz, fOUT= 64 MHz	-	900	1200	µA
J_P	Period jitter peak	fIN= 32 kHz, fOUT= 48 MHz	-	1.5	4	%
		fIN= 32 kHz, fOUT= 64 MHz	-	2.8	7
		fIN= 2 MHz, fOUT= 48 MHz	-	1.3	5
		fIN= 2 MHz, fOUT= 64 MHz	-	3.3	8
t_LOCK	Lock Time	After startup, time to get lock signal. fIN= 32 kHz, fOUT= 64 MHz	-	1.3	2	ms
t_LOCK	Lock Time	After startup, time to get lock signal fIN= 2MHz, fOUT= 64MHz	-	25	50	µs
Duty	Duty cycle	-	40	50	60	%

Table 40-59. FDPLL96M Characteristics⁽¹⁾ (Device Variant B and D)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN	Input frequency	-	32	-	2000	kHz
f_OUT	Output frequency	-	48	-	96	MHz
I_FDPLL96M	Current consumption	fIN= 32 kHz, fOUT= 48 MHz	-	500	740	µA
I_FDPLL96M	Current consumption	fIN= 32 kHz, fOUT= 96 MHz	-	900	1262
J_P	Period jitter peak	fIN= 32 kHz, fOUT= 48 MHz	-	2.1	4	%
		fIN= 32 kHz, fOUT= 96 MHz	-	3.8	11
		fIN= 2 MHz, fOUT= 48 MHz	-	2.2	4
		fIN= 2 MHz, fOUT= 96 MHz	-	5	12
t_LOCK	Lock Time	After startup, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz	-	1.2	2	ms
t_LOCK	Lock Time	fIN= 2 MHz, fOUT= 96 MHz	-	25	50	µs
Duty	Duty cycle	-	40	50	60	%

Note:

SAM D21/DA1 Family