SAM D21/DA1 Family

30.6.4 DMA, Interrupts and Events

Table 30-3. Module Request for TC
Condition	Interrupt request	Event output	Event input	DMA request	DMA request is cleared
Overflow / Underflow	YES	YES		YES	Cleared on next clock cycle
Channel Compare Match or Capture	YES	YES		YES¹	For compare channel – Cleared on next clock cycle. For capture channel – cleared when CCx register is read
Capture Overflow Error	YES
Synchronization Ready	YES
Start Counter			YES
Retrigger Counter			YES
Increment / Decrement counter			YES
Simple Capture			YES
Period Capture			YES
Pulse Width Capture			YES

Note: 1. Two DMA requests lines are available, one for each compare/capture channel.

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