SAM D21/DA1 Family

40.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table 40-49. DFLL48M Characteristics - Open Loop Mode (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 over [-40°, +125°]C, over [2.7, 3.6]V	45	48	49	MHz
f_OUT	Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 at 25°C, over [2.7, 3.6]V	46.5	48	49	MHz
I_DFLL	Power consumption on V_DDIN	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512	-	403	457	µA
t_STARTUP	Startup time	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 f_OUT within 90 % of final value	-	8	12	µs

Table 40-50. DFLL48M Characteristics - Open Loop Mode (Device Variant B and D)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 over [-10°, +125°]C, over [2.7, 3.6]V	44.75	48	49	MHz
f_OUT	Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 over [-40°, +125°]C, over [2.7, 3.6]V	43.5	48	49	MHz
f_OUT	Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 at 25°C, over [2.7, 3.6]V	45.5	48	49	MHz
I_DFLL	Power consumption on V_DDIN	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512	-	403	457	µA
t_STARTUP	Startup time	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 f_OUT within 90 % of final value	-	8	12	µs

Table 40-51. DFLL48M Characteristics - Close Loop Mode (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Average Output frequency	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	47.76	48	48.24	MHz
f_REF	Reference frequency	-	0.732	32.768	33	kHz
Jitter	Cycle to Cycle jitter	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	-	-	0.42	ns
I_DFLL	Power consumption on V_DDIN	f_REF = XTAL, 32 .768kHz, 100ppm	-	403	457	µA
t_LOCK	Lock time	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	-	350	1500	µs

Table 40-52. DFLL48M Characteristics - Close Loop Mode (Device Variant B and D)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Average Output frequency	f_REF= XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	47.76	48	48.24	MHz
f_REF	Reference frequency	-	0.732	32.768	33	kHz
Jitter	Cycle to Cycle jitter	f_REF= XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464	-	-	0.42	ns
I_DFLL	Power consumption on V_DDIN	f_REF = XTAL, 32 .768kHz, 100ppm	-	403	457	µA
t_LOCK	Lock time	f_REF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	-	350	1500	µs

Note: All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop mode with an external OSC reference or the internal OSC8M.

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