10.2 Physical Memory Map

The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follow:

Table 10-1. SAM D21 Physical Memory Map⁽¹⁾⁽¹⁾
Memory	Start address	Size
Memory	Start address	SAMD21x18	SAMD21x17	SAMD21x16	SAMD21x15	SAMD21x16L	SAMD21x15L
Internal Flash	0x00000000	256 Kbytes	128 Kbytes	64 Kbytes	32 Kbytes	64 Kbytes	32 Kbytes
Internal RWWEE Emulation section⁽²⁾	0x00400000	-	4 Kbytes	2 Kbytes	1 Kbytes	2 Kbytes	1 Kbytes
Internal SRAM	0x20000000	32 Kbytes	16 Kbytes	8 Kbytes	4 Kbytes	8 Kbytes	4 Kbytes
Peripheral Bridge A	0x40000000	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes
Peripheral Bridge B	0x41000000	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes
Peripheral Bridge C	0x42000000	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes	64 Kbytes
IOBUS	0x60000000	0.5 Kbytes	0.5 Kbytes	0.5 Kbytes	0.5 Kbytes	0.5 Kbytes	0.5 Kbytes

Table 10-2. SAM DA1 Physical memory map⁽¹⁾
Memory	Start Address	Size
Memory	Start Address	SAMDA1x16	SAMDA1x15	SAMDA1x14
Internal Flash	0x00000000	64Kbytes	32Kbytes	16Kbytes
Internal RWWEE Emulation section	0x00400000	2Kbytes	1Kbytes	512bytes
Internal SRAM	0x20000000	8Kbytes	4Kbytes	4Kbytes
Peripheral Bridge A	0x40000000	64Kbytes	64Kbytes	64Kbytes
Peripheral Bridge B	0x41000000	64Kbytes	64Kbytes	64Kbytes
Peripheral Bridge C	0x42000000	64Kbytes	64Kbytes	64Kbytes

Notes:

1. x = G, J, or E.

2. Only applicable for device variants B, C, D, and L.

Table 10-3. SAM D21 Flash Memory Parameters^(1,2)⁽¹⁾
Device	Flash size	Number of pages	Page size
SAMD21x18	256 Kbytes	4096	64 bytes
SAMD21x17	128 Kbytes	2048	64 bytes
SAMD21x16	64 Kbytes	1024	64 bytes
SAMD21x15	32 Kbytes	512	64 bytes

Table 10-4. SAM DA1 Flash memory parameters⁽¹⁾
Device	Flash Size	Number of Pages	Page Size
SAMDA1x16	64Kbytes	1024	64 bytes
SAMDA1x15	32Kbytes	512	64 bytes
SAMDA1x14	16Kbytes	256	64 bytes

Notes:

1. x = G, J, or E.

2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to NVM Parameter (PARAM) register for details.

Table 10-5. SAM D21 RWWEE Emulation Section Parameters (Device Variants B, C, D,and L)
Device⁽¹⁾	Flash size	Number of pages	Page size
SAMD21x17	4 Kbytes	64	64 bytes
SAMD21x16	2 Kbytes	32	64 bytes
SAMD21x15	1 Kbytes	16	64 bytes

Table 10-6. SAM DA1 RWWEE Emulation Section Parameters
Device	Flash Size	Number of Pages	Page Size
SAMDA1x16	2Kbytes	32	64 bytes
SAMDA1x15	1Kbytes	16	64 bytes
SAMDA1x14	512 bytes	8	64 bytes

Note:

x = G, J, or E.

SAM D21/DA1 Family

10.2 Physical Memory Map