38.6.3 Analog-to-Digital Converter (ADC) Characteristics
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| VDDANA | Power supply voltage | T > 85°C | 2.7 | - | 3.6 | V |
| RES | Resolution | - | 8 | - | 12 | bits |
| fCLK_ADC | ADC Clock frequency | - | 30 | - | 2100 | kHz |
| Sample rate(1) | Single shot | 5 | - | 300 | ksps | |
| Free running | 5 | - | 350 | ksps | ||
| Sampling time(1) | - | 250 | - | - | ns | |
| Sampling time with DAC as input(2) | - | 3 | - | - | µs | |
| Sampling time with Temp sens as input(2) | - | 10 | - | - | µs | |
| Sampling time with Bandgap as input(2) | - | 10 | - | - | µs | |
| Conversion time(1) | 1x Gain | 6 | - | - | cycles | |
| VREF | Voltage reference range (VREFA or VREFB) | - | 1.0 | - | VDDANA-0.6 | V |
| INT1V | Internal 1V reference (2,4) | - | - | 1.0 | - | V |
| INTVCC0 | Internal ratiometric reference 0(2) | - | - | VDDANA/1.48 | - | V |
| INTVCC0 Voltage Error | Internal ratiometric reference 0(2) error | 2.0V < VDDANA<3.63V | -1.0 | - | +1.0 | % |
| INTVCC1 | Internal ratiometric reference 1(2) | VDDANA>2.0V | - | VDDANA/2 | - | V |
| INTVCC1 Voltage Error | Internal ratiometric reference 1(2) error | 2.0V < VDDANA<3.63V | -1.0 | - | +1.0 | % |
| Conversion range(1) | Differential mode | -VREF/GAIN | - | +VREF/GAIN | V | |
| Single-ended mode | 0.0 | - | +VREF/GAIN | V | ||
| CSAMPLE | Sampling capacitance(2) | - | - | 3.5 | - | pF |
| RSAMPLE | Input channel source resistance(2) | - | - | - | 3.5 | kΩ |
| IDD | DC supply current(1) | fCLK_ADC = 2.1-MHz(3) | - | 1.25 | 1.83 | mA |
- These values are based on characterization. These values are not covered by test limits in production.
- These values are based on simulation. These values are not covered by test limits in production or characterization.
- In this condition and for a sample rate of 350ksps, a conversion takes 6 clock cycles of the ADC clock (conditions: 1X gain, 12-bit resolution, differential mode, free-running).
- It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| ENOB | Effective Number Of Bits | With gain compensation | - | 10.5 | 10.8 | bits |
| TUE | Total Unadjusted Error | 1x Gain | 1.5 | 2.7 | 13 | LSB |
| INL | Integral Non Linearity | 1x Gain | 0.9 | 1.3 | 4 | LSB |
| DNL | Differential Non Linearity | 1x Gain | +/-0.3 | +/-0.5 | +/-0.95 | LSB |
| GE | Gain Error | Ext. Ref 1x | -10.0 | -1.3 | +10.0 | mV |
| VREF = VDDANA/1.48 | -20.0 | -10.0 | +10.0 | mV | ||
| VREF = INT1V | -20.0 | +2 | +20.0 | mV | ||
| Gain Accuracy(5) | Ext. Ref. 0.5x | +/-0.02 | +/-0.05 | +/-0.2 | % | |
| Ext. Ref. 2x to 16x | +/-0.01 | +/-0.03 | +/-0.5 | % | ||
| OE | Offset Error | Ext. Ref. 1x | -8.0 | -1.0 | +8.0 | mV |
| VREF = VDDANA/1.48 | -8.0 | -0.60 | +8.0 | mV | ||
| VREF = INT1V | -6.0 | -1.0 | +6.0 | mV | ||
| SFDR | Spurious Free Dynamic Range | 1x Gain FCLK_ADC = 2.1 MHz FIN = 40 kHz AIN = 95% FSR | 65.0 | 71.5 | 76.0 | dB |
| SINAD | Signal-to-Noise and Distortion | 58.0 | 65.0 | 67.0 | dB | |
| SNR | Signal-to-Noise Ratio | 60.0 | 66.0 | 68.6 | dB | |
| THD | Total Harmonic Distortion | -75.0 | -71.0 | -67.0 | dB | |
| Noise RMS | T = 25°C | 0.6 | 1.0 | 1.6 | mV |
- Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range.
- Dynamic parameter numbers are based on characterization and not tested in production.
- Respect the input common mode voltage
through the following equations (where, VCM_IN is the Input channel common mode
voltage):
- If |VIN| > VREF/4
- VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
- VCM_IN > VREF/4 -0.05*VDDANA -0.1V
- If |VIN| < VREF/4
- VCM_IN < 1.2*VDDANA - 0.75V
- VCM_IN > 0.2*VDDANA - 0.1V
- If |VIN| > VREF/4
- The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
- The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN)
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| ENOB | Effective Number of Bits | With gain compensation | - | 9.7 | 10.1 | Bits |
| TUE | Total Unadjusted Error | 1x gain | - | 7.9 | 30.0 | LSB |
| INL | Integral Non-Linearity | 1x gain | 1.4 | 2.6 | 5.0 | LSB |
| DNL | Differential Non-Linearity | 1x gain | +/-0.6 | +/-0.7 | +/-0.95 | LSB |
| GE | Gain Error | Ext. Ref. 1x | -5.0 | 0.6 | 5.0 | mV |
| Gain Accuracy(4) | Ext. Ref. 0.5x | +/-0.1 | +/-0.37 | +/-0.5 | % | |
| Ext. Ref. 2x to 16X | +/-0.01 | +/-0.1 | +/-0.2 | % | ||
| OE | Offset Error | Ext. Ref. 1x | -5.0 | 0.6 | 10.0 | mV |
| SFDR | Spurious Free Dynamic Range | 1x Gain FCLK_ADC = 2.1 MHz FIN = 40 kHz AIN = 95% FSR | 63.0 | 68.0 | 70.1 | dB |
| SINAD | Signal-to-Noise and Distortion | 55.0 | 60.1 | 62.5 | dB | |
| SNR | Signal-to-Noise Ratio | 54.0 | 61.0 | 64.0 | dB | |
| THD | Total Harmonic Distortion | -70.0 | -68.0 | -65.0 | dB | |
| Noise RMS | T = 25°C | - | 1.0 | - | mV |
- Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range.
- Respect the input common mode voltage through the following equations (where VCM_IN is
the Input channel common mode voltage) for all VIN:
- VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
- VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
- The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
- The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (Vref/GAIN)