17.8.4 Power and Clocks Status
| Name: | PCLKSR |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPLLLTO | DPLLLCKF | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DPLLLCKR | B33SRDY | BOD33DET | BOD33RDY | DFLLRCS | |||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | OSC8MRDY | OSC32KRDY | XOSC32KRDY | XOSCRDY | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 17 – DPLLLTO DPLL Lock Time-out
| Value | Description |
|---|---|
| 0 | DPLL Lock time-out not detected |
| 1 | DPLL Lock time-out detected |
Bit 16 – DPLLLCKF DPLL Lock Fall
| Value | Description |
|---|---|
| 0 | DPLL Lock fall edge not detected |
| 1 | DPLL Lock fall edge detected |
Bit 15 – DPLLLCKR DPLL Lock Rise
| Value | Description |
|---|---|
| 0 | DPLL Lock rise edge not detected |
| 1 | DPLL Lock fall edge detected |
Bit 11 – B33SRDY BOD33 Synchronization Ready
| Value | Description |
|---|---|
| 0 | BOD33 synchronization is complete |
| 1 | BOD33 synchronization is ongoing |
Bit 10 – BOD33DET BOD33 Detection
| Value | Description |
|---|---|
| 0 | No BOD33 detection |
| 1 | BOD33 has detected that the I/O power supply is going below the BOD33 reference value |
Bit 9 – BOD33RDY BOD33 Ready
| Value | Description |
|---|---|
| 0 | BOD33 is not ready |
| 1 | BOD33 is ready |
Bit 8 – DFLLRCS DFLL Reference Clock Stopped
| Value | Description |
|---|---|
| 0 | DFLL reference clock is running |
| 1 | DFLL reference clock has stopped |
Bit 7 – DFLLLCKC DFLL Lock Coarse
| Value | Description |
|---|---|
| 0 | No DFLL coarse lock detected |
| 1 | DFLL coarse lock detected |
Bit 6 – DFLLLCKF DFLL Lock Fine
| Value | Description |
|---|---|
| 0 | No DFLL fine lock detected |
| 1 | DFLL fine lock detected |
Bit 5 – DFLLOOB DFLL Out Of Bounds
| Value | Description |
|---|---|
| 0 | No DFLL Out Of Bounds detected |
| 1 | DFLL Out Of Bounds detected |
Bit 4 – DFLLRDY DFLL Ready
| Value | Description |
|---|---|
| 0 | The synchronization is ongoing |
| 1 | The synchronization is complete |
Bit 3 – OSC8MRDY OSC8M Ready
| Value | Description |
|---|---|
| 0 | OSC8M is not ready |
| 1 | OSC8M is stable and ready to be used as a clock source |
Bit 2 – OSC32KRDY OSC32K Ready
| Value | Description |
|---|---|
| 0 | OSC32K is not ready |
| 1 | OSC32K is stable and ready to be used as a clock source |
Bit 1 – XOSC32KRDY XOSC32K Ready
| Value | Description |
|---|---|
| 0 | XOSC32K is not ready |
| 1 | XOSC32K is stable and ready to be used as a clock source |
Bit 0 – XOSCRDY XOSC Ready
| Value | Description |
|---|---|
| 0 | XOSC is not ready |
| 1 | XOSC is stable and ready to be used as a clock source |