SAM D21/DA1 Family

41.12.3 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table 41-41. DFLL48M Characteristics - Open Loop Mode
Parameter	Conditions	Symbol	Min.	Typ.	Max.	Unit
Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 over [–10, +105]C, over [2.7, 3.6]V	f_OUT	44.75	48	49	MHz
Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 over [–40, +105]C, over [2.7, 3.6]V	f_OUT	43.75	48	49	MHz
Output frequency	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 at 25°C, over [2.7, 3.6]V	f_OUT	45.5	48	49	MHz
Power consumption on V_DDIN	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512	I_DFLL	-	403	453	μA
Startup time	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 f_OUTwithin 90 % of final value	t_STARTUP	-	8.6	11.5	μs

Table 41-42. DFLL48M Characteristics - Closed Loop Mode⁽¹⁾
Parameter	Conditions	Symbol	Min.	Typ.	Max.	Unit
Average Output frequency	f_REF = XTAL, 32.768kHz, 100ppm DFLLMUL = 1464	f_CloseOUT	47.963	47.972	47.981	MHz
Reference frequency		f_REF	0.732	32.768	33	kHz
Cycle to Cycle jitter	f_REF = XTAL, 32.768kHz, 100ppm DFLLMUL = 1464	Jitter	-	-	0.42	ns
Power consumption on V_DDIN	f_REF = XTAL, 32.768kHz, 100ppm	I_DFLL	-	403	453	μA
Lock time	f_REF = XTAL, 32.768kHz, 100ppm DFFLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	t_LOCK	-	350	1500	μs

Note:

All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop mode with an external OSC reference or the internal OSC8M.
To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy.

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