34.8.8 Status B

Name: STATUSB
Offset: 0x09
Reset: 0x00
Property: 

Bit 76543210 
 SYNCBUSY     READY1READY0 
Access RRR 
Reset 000 

Bit 7 – SYNCBUSY Synchronization Busy

This bit is cleared when the synchronization of registers between the clock domains is complete.

This bit is set when the synchronization of registers between clock domains is started.

Bits 0, 1 – READYx Comparator x Ready

This bit is cleared when the comparator x output is not ready.
 This bit is set when the comparator x output is ready.

If comparator x is not implemented, READYx always reads as zero.