32.19.7 Host Pipe Interrupt Clear Register
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or if the endpoint is disabled.
| Name: | PINTENCLR |
| Offset: | 0x108 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STALL | TXSTP | PERR | TRFAIL | TRCPT1 | TRCPT0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – STALL Received Stall Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The received Stall interrupt is disabled. |
| 1 | The received Stall interrupt is enabled and an interrupt request will be generated when the received Stall interrupt Flag is set. |
Bit 4 – TXSTP Transmitted Setup Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transmitted Setup interrupt is disabled. |
| 1 | The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the Transmitted Setup interrupt Flag is set. |
Bit 3 – PERR Pipe Error Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Pipe Error interrupt is disabled. |
| 1 | The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error interrupt Flag is set. |
Bit 2 – TRFAIL Transfer Fail Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transfer Fail interrupt is disabled. |
| 1 | The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt Flag is set. |
Bits 0, 1 – TRCPT Transfer Complete Bank x interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit x and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Transfer Complete Bank x interrupt is disabled. |
| 1 | The Transfer Complete Bank x interrupt is enabled and an interrupt request will be generated when the Transfer Complete interrupt x Flag is set. |