31.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

• The Software Reset and Enable bits in the Control A register (CTRLA.SWRST and CTRLA.ENABLE)

The following registers are synchronized when written:

• The Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
• The Status register (STATUS)
• The Pattern and Pattern Buffer registers (PATT and PATTB)
• The Waveform register (WAVE)
• The Count Value register (COUNT)
• The Period Value and Period Buffer Value registers (PER and PERB)
• The Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBx)

The following registers are synchronized when read:

• The Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
• The Count Value register (COUNT): synchronization is done on demand through READSYNC command (CTRLBSET.CMD)

Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.

Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.