10.1 Overview
The following table provides the configuration for the Arm Cortex-M33 processor in the PIC32CK SG/GC devices.
Features | Configuration |
---|---|
Debug | |
Comparator set | Full comparator set: 4 DWT and 8 FPB comparators |
ETM support | Instruction ETM interface |
Internal Trace support (ITM) | ITM and DWT trace functionality implemented |
CTI and WIC | Not embedded |
TCM | |
ITCM maximum size | 128 KB |
DTCM maximum size | 128 KB |
Cache | |
Cache size | 16 KB for instruction cache, 16 KB for data cache |
Number of sets | 256 for instruction cache, 128 for data cache |
Number of ways | 2 for instruction cache, 4 for data cache |
Number of words per cache line | 8 words (32 bytes) |
ECC on Cache | Embedded |
NVIC | |
IRQ number | 158 |
IRQ priority levels | 8 |
MPU | |
Number of regions | 8 |
FPU | |
FPU precision | Single precision |