32.4 Peripheral Dependencies
| Peripheral Name | Base Address | NVIC IRQ Index: Source | MCLK AHBx/APBx Clock Enable Mask Bit | GCLK Peripheral Channel Clock Name:Register | PAC Peripheral Identifier
(PAC.WRCTRL.PERIDx) | Power Domain |
|---|---|---|---|---|---|---|
| EVSYS | 0x4480_E000 | 39 : EVD_0, OVR_0 40 : EVD_1, OVR_1 41 : EVD_2, OVR_2 42 : EVD_3, OVR_3 43 : EVD_4, OVR_4, EVD_5, OVR_5, EVD_6, OVR_6, EVD_7, OVR_7, EVD_8, OVR_8, EVD_9, OVR_9, EVD_10, OVR_10, EVD_11, OVR_11, NSCHK | MCLK.CLKMSK2[6] |
GCLK_EVSYS_CH0 : GCLK.PCHCTRL[6] GCLK_EVSYS_CH1 : GCLK.PCHCTRL[7] GCLK_EVSYS_CH2 : GCLK.PCHCTRL[8] GCLK_EVSYS_CH3 : GCLK.PCHCTRL[9] GCLK_EVSYS_CH4 : GCLK.PCHCTRL[10] GCLK_EVSYS_CH5 : GCLK.PCHCTRL[11] GCLK_EVSYS_CH6 : GCLK.PCHCTRL[12] GCLK_EVSYS_CH7 : GCLK.PCHCTRL[13] GCLK_EVSYS_CH8 : GCLK.PCHCTRL[14] GCLK_EVSYS_CH9 : GCLK.PCHCTRL[15] GCLK_EVSYS_CH10 : GCLK.PCHCTRL[16] GCLK_EVSYS_CH11 : GCLK.PCHCTRL[17] | 27 | VDDCORE_SW |