34.4 Peripheral Dependencies

Peripheral

Name

Base AddressNVIC IRQ Index: SourceMCLK AHBx/APBx

Clock Enable Mask Bit

GCLK Peripheral Channel

Clock Name:Register

PAC Peripheral Identifier

(PAC.WRCTRL.PERIDx)

DMA Trigger Index:Source

(DMAC.CHCTRLBk.TRIGx)

Power

Domain

FIFO Size
SERCOM00x4481_000044 : ERROR, RXBRK

45 : DRE/PREC

46 : TXC/AMATCH

47 : RXC/DRDY

48 : RXS/SSL/TXFE

49 : CTSIC/RXFF

MCLK.CLKMKS2[7]

GCLK_SERCOM0_SLOW: GCLK.PCHCTRL[18]

GCLK_SERCOM0_CORE : GCLK.PCHCTRL[19]

285 : RX

6 : TX

VDDCORE_SW16 Bytes
SERCOM10x4481_200050 : ERROR, RXBRK

51 : DRE/PREC

52 : TXC/AMATCH

53 : RXC/DRDY

54 : RXS/SSL/TXFE

55 : CTSIC/RXFF

MCLK.CLKMKS2[8]

GCLK_SERCOM1_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM1_CORE : GCLK.PCHCTRL[20]

297 : RX

8 : TX

VDDCORE_SW8 Bytes
SERCOM20x4481_400056 : ERROR, RXBRK

57 : DRE/PREC

58 : TXC/AMATCH

59 : RXC/DRDY

60 : RXS/SSL/TXFE

61 : CTSIC/RXFF

MCLK.CLKMKS2[9]

GCLK_SERCOM2_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM2_CORE : GCLK.PCHCTRL[21]

309 : RX

10 : TX

VDDCORE_SW8 Bytes
SERCOM30x4481_600062 : ERROR, RXBRK

63 : DRE/PREC

64 : TXC/AMATCH

65 : RXC/DRDY

66 : RXS/SSL/TXFE

67 : CTSIC/RXFF

MCLK.CLKMKS2[10]

GCLK_SERCOM3_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM3_CORE : GCLK.PCHCTRL[22]

3111 : RX

12 : TX

VDDCORE_SW8 Bytes
SERCOM40x4500_000096 : ERROR, RXBRK

97 : DRE/PREC

98 : TXC/AMATCH

99 : RXC/DRDY

100 : RXS/SSL/TXFE

101 : CTSIC/RXFF

MCLK.CLKMKS3[0]

GCLK_SERCOM4_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM4_CORE : GCLK.PCHCTRL[25]

3641 : RX

42 : TX

VDDCORE_SW8 Bytes
SERCOM50x4500_2000102 : ERROR, RXBRK

103 : DRE/PREC

104 : TXC/AMATCH

105 : RXC/DRDY

106 : RXS/SSL/TXFE

107 : CTSIC/RXFF

MCLK.CLKMKS3[1]

GCLK_SERCOM5_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM5_CORE : GCLK.PCHCTRL[26]

3743 : RX

44 : TX

VDDCORE_SW8 Bytes
SERCOM60x4500_4000108 : ERROR, RXBRK

109 : DRE/PREC

110 : TXC/AMATCH

111 : RXC/DRDY

112 : RXS/SSL/TXFE

113 : CTSIC/RXFF

MCLK.CLKMKS3[2]

GCLK_SERCOM6_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM6_CORE : GCLK.PCHCTRL[27]

3845 : RX

46 : TX

VDDCORE_SW8 Bytes
SERCOM70x4500_8000114 : ERROR, RXBRK

115 : DRE/PREC

116 : TXC/AMATCH

117 : RXC/DRDY

118 : RXS/SSL/TXFE

119 : CTSIC/RXFF

MCLK.CLKMKS3[3]

GCLK_SERCOM7_SLOW : GCLK.PCHCTRL[18]

GCLK_SERCOM7_CORE : GCLK.PCHCTRL[28]

3947 : RX

48 : TX

VDDCORE_SW8 Bytes

I/O Lines

Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI and USART are routed through these SERCOM pads through a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode specific sections below for additional information.

Power Management

The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM interrupts can be configured to wake the device from sleep modes.

Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. The SERCOM APB BUS interface clocks are enabled by default on reset.

The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a host. The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode sections below for details.

These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM.

The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to Synchronization for details.

DMA

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used.

Concurrent DMA and CPU accesses to the DATA register must be avoided, as this may lead to unpredictable behavior.

Debug Operation

When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL) register for details.

Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

  • Interrupt Flag Clear and Status register (INTFLAG)
  • Status register (STATUS)
  • Data register (DATA)
  • Address register (ADDR)

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description.

PAC write protection does not apply to accesses through an external debugger.