51.19 Analog-to-Digital Converter (ADC) Electrical Specifications

Table 51-24. ADC AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
Device Supply
ADC_1AVDDADC Module SupplyAVDD(min)AVDD(max)VVDDIOx = AVDD
Reference Inputs
ADC_3VREF(4)ADC Reference Voltage (4)The greater of ≥ AVDD(min) or 2.4V (4)AVDD V VREF ≤ AVDD
Analog Input Range
ADC_7AFSFull-Scale Analog Input Signal Range (Single-Ended)AVSSVREF VVREF = AVDD(max)
ADC_9Full-Scale Analog Input Signal Range (Differential)-VREFVREF V
Note:
  1. Characterized with an analog input sine wave = (FTP(max)/100). For example: FTP(max) = 1 Msps /100 = 10 kHz sine wave.
  2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12bit resolution.
  3. ADC is configured in 12-bits mode, All registers are at the reset default value unless otherwise stated.
  4. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~ ((0,006 * 2^n)/VREF) LSB’s over full scale range, where "n" = #bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on AVDD, AVSS.
  5. Value taken over 7 harmonics.
  6. Value coming from simulation.
Table 51-25. ADC Single Ended Mode AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
SINGLE ENDED MODE ADC Accuracy
SADC_11ResResolution812bitsSelectable 8, 10, 12 bit Resolution Ranges
SADC_13INL (3)Integral Nonlinearity-2±1.252LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_19DNL (3)Differential Nonlinearity-1-0.75 / +12LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_25GERR (3,6)Gain Error-5-1LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_31E0FF (3,6)0ffset Error14LSB3.125 Msps Internal VREF = AVDD = VDDIO = 3.3V
SINGLE ENDED MODE ADC Dynamic Performance (1,2)
SADC_43EN0B (3)Effective Number of bits10.611.2bitsVREF = AVDD = VDDIO = 3.3V @ 12 bit at 3.125 Msps
SADC_45SINAD (1,2,3)Signal to Noise and Distortion6570dB
SADC_47SNR (1,2,3)Signal to Noise ratio6570
SADC_51THD (1,2,3,5)Total Harmonic Distortion-80-75
Note:
  1. Characterized with an analog input sine wave = (FTP(max) /100). For example: FTP(max) = 1 Msps/100 = 10 kHz sine wave.
  2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution.
  3. ADC is configured in 12 bits mode, All registers are at the reset default value unless otherwise stated.
  4. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~ ((0,006 * 2^n) / VREF) LSB’s over full scale range, where "n" = #bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on AVDD and AVSS.
  5. Value taken over 7 harmonics.
  6. Value coming from simulation.
Table 51-26. ADC Differential Mode AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
DIFFERENTIAL MODE ADC Accuracy
DADC_11ResResolution812bitsSelectable 8, 10, 12 bit Resolution Ranges
DADC_13INL (3)Integral Nonlinearity-2±1.252LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DADC_19DNL (3)Differential Nonlinearity-1-0.75 / +12LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DADC_25GERR (3,6)Gain Error-5-1LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DADC_31E0FF (3,6)0ffset Error12LSB3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DIFFERENTIAL MODE ADC Dynamic Performance (1,2)
DADC_43EN0B (3)Effective Number of bits11.211.4bitsVREF = AVDD = VDDIO = 3.3V @ 12 bit at 3.125 Msps
DADC_45SINAD (1,2,3)Signal to Noise and Distortion6870dB
DADC_47SNR (1,2,3)Signal to Noise ratio6870
DADC_51THD (1,2,3,5)Total Harmonic Distortion-84-80
Note:
  1. Characterized with an analog input sine wave = (FTP(max) /100). Example: FTP(max) = 1 Msps/100 = 10 kHz sine wave.
  2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12bit resolution.
  3. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~ ((0,006 * 2^n) / VREF) LSB’s over full scale range, where "n" = #bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on AVDD and AVSS.
  4. Value taken over 7 harmonics.
  5. Value coming from simulation.
Table 51-27. ADC Conversion and Sample AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
ADC Clock Requirements
ADC_53TADADC Clock Period207145nsVREF = AVDD = 3.3V and Res = 6, 8, 10 bit
201250nsVREF = AVDD = 3.3V and Res = 12 bit
ADC_55fGCLK_ADCxADCx Module GCLK max input freqFCLK_51MHzVREF = AVDD = 3.3V
ADC Throughput Rates
ADC_57FTPR (1)Sample-Rate for ADC with SAMC=1 (min)3.125Msps12-bit resolution, Rsource Impedance ≤ 200 Ω
3.57142910-bit resolution, Rsource Impedance ≤ 250 Ω
4.1666678-bit resolution, Rsource Impedance ≤ 300 Ω
56-bit resolution, Rsource Impedance ≤ 400 Ω
ADC Conversion and Sample Time
ADC_59TSAMPSample-Time for ADC3TAD12 bit TAD(min), Ext Analog Input Rsource ≤ 200 Ω, Max ADC Clock
310 bit TAD(min), Ext Analog Input Rsource ≤ 250 Ω, Max ADC Clock
812 bit TAD(min), Ext Analog Input Rsource ≤ 500 Ω, Max ADC Clock
810 bit TAD(min), Ext Analog Input Rsource ≤ 700 Ω, Max ADC Clock
1412 bit TAD(min), Ext Analog Input Rsource ≤ 1 kΩ, Max ADC Clock
1410 bit TAD(min), Ext Analog Input Rsource ≤ 1.25 kΩ, Max ADC Clock
6412 bit TAD(min), Ext Analog Input Rsource ≤ 5 kΩ, Max ADC Clock
6410 bit TAD(min), Ext Analog Input Rsource ≤ 5.5 kΩ, Max ADC Clock
ADC_61TCNVConversion Time (after sample time is complete)13TAD12-bit resolution
1110-bit resolution
98-bit resolution
76-bit resolution
ADC_63Twarm-upWarm Up Time after CTRLA.ANAEN = 1 and CTRLA.ENABLE = 1 500 TAD or 20 µs, which ever is biggerµs
Note:
  1. ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (Number of user active analog inputs in use on specific target ADC module)).

    Specification values assume only one AINx channel in use.