51.3 Power Supply
DC CHARACTERISTICS | Standard
Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
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Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
REG_5 | VDDIOx_CIN (4) | VDDIOx Input Bypass parallel Capacitor pair | 33 | — | — | µF | Bulk Ceramic or solid Tantalum with ESR <0.5Ω |
100 | — | — | nF | Ceramic X7R with ESR <0.5Ω on all VDDIOx pins | |||
REG_6 | VDDREG_CIN (4) | VDDREGx Input Bypass parallel Capacitor pair | 33 | — | — | µF | Bulk Ceramic or solid Tantalum with ESR <0.5Ω |
100 | — | — | nF | Ceramic X7R with ESR <0.5Ω on all VDDIOx pins | |||
REG_10 | VDDUSB_CIN (4) | USB Power pin bypass capacitance | 4.7 | — | — | µF | Required VDDUSB power pin paralell bypass capacitors |
0.1 | — | — | µF | ||||
REG_17 | AVDD_CIN (4) | AVDD Input Bypass parallel Capacitor pair | 10 | — | — | µF | Bulk Ceramic or solid Tantalum with ESR <0.5Ω |
100 | — | — | nF | Ceramic X7R with ESR <0.5Ω | |||
REG_23 | AVDD_LEXT (1) | AVDD series Ferrite Bead DCR (DC Resistance) | — | — | 0.15 | Ω | ≥1k Ω @ 100 MHz |
REG_25 | Ferrite Bead current Rating | 500 | — | — | mA | — | |
REG_37 | VDDIOx (2) | VDDIO Input Voltage Range | 1.71 | 3.3 | 3.63 | V | — |
REG_39 | AVDD (2) | AVDD Input Voltage Range | 1.71 | 3.3 | 3.63 | V | — |
REG_40 | VDDREG (3) | VDDREG Input Voltage Range | 1.71 | 3.3 | 3.63 | V | — |
REG_42 | VDDUSB | VDDUSB Input Voltage Range | 3 | — | 3.6 | V | — |
REG_42A | IDDUSB | VUSB3V3 max current | — | — | 8 | mA | — |
REG_43 | SVDD_R | VDD Rise Ramp Rate to Ensure Internal Power-on Reset Signal | 0.00000033 | — | 0.18 | V/µs | Failure to meet this specification may lead to start-up or unexpected behaviors |
REG_45 | VPOR | Power-on Reset | 1.43 | — | — | V | VDD Power-down |
REG_47 | VDDIO / AVDD BOR (5) | VDDIO / AVDD Brown-Out Reset Thresholds | 1.63 | — | 1.7 | V | BOR_TRIP_VDDx = 0x0 (6)
HYST_BOR_VDDx = 0x0 |
2.11 | — | 2.24 | V | BOR_TRIP_VDDx = 0x1 HYST_BOR_VDDx = 0x0 | |||
2.49 | — | 2.68 | V | BOR_TRIP_VDDx = 0x2 HYST_BOR_VDDx = 0x0 | |||
2.75 | — | 2.97 | V | BOR_TRIP_VDDx = 0x3 HYST_BOR_VDDx = 0x0 | |||
1.61 | — | 1.7 | V | BOR_TRIP_VDDx = 0x0 (6)
HYST_BOR_VDDx = 0x1 | |||
2.05 | — | 2.24 | V | BOR_TRIP_VDDx = 0x1 HYST_BOR_VDDx = 0x1 | |||
2.41 | — | 2.68 | V | BOR_TRIP_VDDx = 0x2 HYST_BOR_VDDx = 0x1 | |||
2.62 | — | 2.97 | V | BOR_TRIP_VDDx = 0x3 HYST_BOR_VDDx = 0x1 | |||
REG_49 | VDDREG BOR (5) | VDDREG Brown-Out Reset Thresholds | 1.63 | — | 1.7 | V | HYST_BOR_VDDREG = 0x0 (6) |
1.61 | — | 1.7 | V | HYST_BOR_VDDREG = 0x1 (6) | |||
REG_50 | VDDUSB BOR (5) | VDDUSB Brown-Out Reset Thresholds | 2.75 | — | 2.97 | V | — |
REG_51 | VDDIO / AVDD / VDDREG DCBOR (7) | VDDIO / AVDD / VDDREG Duty Cycled BOR Thresholds | 1.44 | — | — | V | BOR_TRIP = 0x0 BOR_HYS = 0x0 |
1.88 | — | — | V | BOR_TRIP = 0x1 BOR_HYS = 0x0 | |||
2.23 | — | — | V | BOR_TRIP = 0x2 BOR_HYS = 0x0 | |||
2.43 | — | — | V | BOR_TRIP = 0x3 BOR_HYS = 0x0 | |||
1.41 | — | — | V | BOR_TRIP = 0x0 BOR_HYS = 0x1 | |||
1.81 | — | — | V | BOR_TRIP = 0x1 BOR_HYS = 0x1 | |||
2.14 | — | — | V | BOR_TRIP = 0x2 BOR_HYS = 0x1 | |||
2.27 | — | — | V | BOR_TRIP = 0x3 BOR_HYS = 0x1 | |||
REG_52 | LVD (8) | VDDIO Low Voltage Detector Thresholds | 1.66 | — | 1.76 | V | LVD.LEVEL = 0x0 |
1.74 | — | 1.84 | V | LVD.LEVEL = 0x1 | |||
1.82 | — | 1.92 | V | LVD.LEVEL = 0x2 | |||
1.96 | — | 2.07 | V | LVD.LEVEL = 0x3 | |||
2.06 | — | 2.18 | V | LVD.LEVEL = 0x4 | |||
2.11 | — | 2.24 | V | LVD.LEVEL = 0x5 | |||
2.17 | — | 2.30 | V | LVD.LEVEL = 0x6 | |||
2.25 | — | 2.37 | V | LVD.LEVEL = 0x7 | |||
2.32 | — | 2.44 | V | LVD.LEVEL = 0x8 | |||
2.43 | — | 2.55 | V | LVD.LEVEL = 0x9 | |||
2.63 | — | 2.77 | V | LVD.LEVEL = 0xA | |||
2.72 | — | 2.87 | V | LVD.LEVEL = 0xB | |||
2.82 | — | 2.97 | V | LVD.LEVEL = 0xC | |||
2.93 | — | 3.08 | V | LVD.LEVEL = 0xD | |||
3.24 | — | 3.40 | V | LVD.LEVEL = 0xE | |||
3.54 | — | 3.71 | V | LVD.LEVEL = 0xF | |||
REG_53 | TRST | External RESET valid active pulse width | 2 | — | — | µs | Minimum reset active time to guarantee MCU reset |
Note:
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