51.3 Power Supply

Table 51-6. Power Supply DC Electrical Specifications
DC CHARACTERISTICSStandard Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
REG_5VDDIOx_CIN (4)VDDIOx Input Bypass parallel Capacitor pair33µFBulk Ceramic or solid Tantalum with ESR <0.5Ω
100nFCeramic X7R with ESR <0.5Ω on all VDDIOx pins
REG_6VDDREG_CIN (4)VDDREGx Input Bypass parallel Capacitor pair33µFBulk Ceramic or solid Tantalum with ESR <0.5Ω
100nFCeramic X7R with ESR <0.5Ω on all VDDIOx pins
REG_10VDDUSB_CIN (4)USB Power pin bypass capacitance4.7µFRequired VDDUSB power pin paralell bypass capacitors
0.1µF
REG_17AVDD_CIN (4)AVDD Input Bypass parallel Capacitor pair10µFBulk Ceramic or solid Tantalum with ESR <0.5Ω
100nFCeramic X7R with ESR <0.5Ω
REG_23AVDD_LEXT (1)AVDD series Ferrite Bead DCR (DC Resistance)0.15≥1k Ω @ 100 MHz
REG_25Ferrite Bead current Rating500mA
REG_37VDDIOx (2)VDDIO Input Voltage Range1.713.33.63V
REG_39AVDD (2)AVDD Input Voltage Range1.713.33.63V
REG_40VDDREG (3)VDDREG Input Voltage Range1.713.33.63V
REG_42VDDUSBVDDUSB Input Voltage Range33.6V
REG_42AIDDUSBVUSB3V3 max current8mA
REG_43SVDD_RVDD Rise Ramp Rate to Ensure Internal Power-on Reset Signal0.000000330.18V/µsFailure to meet this specification may lead to start-up or unexpected behaviors
REG_45VPORPower-on Reset 1.43V VDD Power-down
REG_47VDDIO / AVDD BOR (5)VDDIO / AVDD Brown-Out Reset Thresholds1.631.7VBOR_TRIP_VDDx = 0x0 (6)

HYST_BOR_VDDx = 0x0

2.112.24VBOR_TRIP_VDDx = 0x1

HYST_BOR_VDDx = 0x0

2.492.68VBOR_TRIP_VDDx = 0x2

HYST_BOR_VDDx = 0x0

2.752.97VBOR_TRIP_VDDx = 0x3

HYST_BOR_VDDx = 0x0

1.611.7VBOR_TRIP_VDDx = 0x0 (6)

HYST_BOR_VDDx = 0x1

2.052.24VBOR_TRIP_VDDx = 0x1

HYST_BOR_VDDx = 0x1

2.412.68VBOR_TRIP_VDDx = 0x2

HYST_BOR_VDDx = 0x1

2.622.97VBOR_TRIP_VDDx = 0x3

HYST_BOR_VDDx = 0x1

REG_49VDDREG BOR (5)VDDREG Brown-Out Reset Thresholds1.631.7VHYST_BOR_VDDREG = 0x0 (6)
1.611.7VHYST_BOR_VDDREG = 0x1 (6)
REG_50VDDUSB BOR (5)VDDUSB Brown-Out Reset Thresholds2.752.97V
REG_51VDDIO / AVDD / VDDREG DCBOR (7)VDDIO / AVDD / VDDREG Duty Cycled BOR Thresholds1.44VBOR_TRIP = 0x0

BOR_HYS = 0x0

1.88VBOR_TRIP = 0x1

BOR_HYS = 0x0

2.23VBOR_TRIP = 0x2

BOR_HYS = 0x0

2.43VBOR_TRIP = 0x3

BOR_HYS = 0x0

1.41VBOR_TRIP = 0x0

BOR_HYS = 0x1

1.81VBOR_TRIP = 0x1

BOR_HYS = 0x1

2.14VBOR_TRIP = 0x2

BOR_HYS = 0x1

2.27VBOR_TRIP = 0x3

BOR_HYS = 0x1

REG_52LVD (8)VDDIO Low Voltage Detector Thresholds1.661.76VLVD.LEVEL = 0x0
1.741.84VLVD.LEVEL = 0x1
1.821.92VLVD.LEVEL = 0x2
1.962.07VLVD.LEVEL = 0x3
2.062.18VLVD.LEVEL = 0x4
2.112.24VLVD.LEVEL = 0x5
2.172.30VLVD.LEVEL = 0x6
2.252.37VLVD.LEVEL = 0x7
2.322.44VLVD.LEVEL = 0x8
2.432.55VLVD.LEVEL = 0x9
2.632.77VLVD.LEVEL = 0xA
2.722.87VLVD.LEVEL = 0xB
2.822.97VLVD.LEVEL = 0xC
2.933.08VLVD.LEVEL = 0xD
3.243.40VLVD.LEVEL = 0xE
3.543.71VLVD.LEVEL = 0xF
REG_53TRSTExternal RESET valid active pulse width2µsMinimum reset active time to guarantee MCU reset
Note:
  1. Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15).
  2. VDDIOx and AVDD must be at the same voltage level.
  3. VDDREG voltage must be equal or lower than VDDIOx.
  4. All bypass caps should be located immediately adjacent to pin(s) and on the same side of the PCB as the MCU, or in the case of BGA packages, directly below the power pads and direct adjacent to the fan-out vias. Each primary power supply group VDDIO and AVDD should have one bulk capacitor and all power pins everywhere a 100 nF bypass cap.
  5. Voltages below the Min BOR threshold will result in a device reset, except for the BOR_VDDUSB that can cause an interrupt. Voltages above the Max BOR threshold will allow the device starting-up.
  6. Overall functional device operation at VBORMIN < VDD < VDDMIN is guaranteed, but not characterized. Device will function with degraded performances below VDDMIN.
  7. Voltages below the Min DCBOR threshold will result in a device reset.
  8. Voltages below the Min LVD threshold will result in a falling detection. Voltages above the Max LVD threshold will result in a rising detection. Enabling the LVD when VDDIO is between Min / Max thresholds may result in unexpected behavior.