51.18 DFLL/PLL Electrical Specifications

Table 51-22. DFLL (Digital Frequency Locked Loop) AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
DFLL48MHz (Open Loop) (1,2)
DFLL_1DFLL_OL_FOUTDFLL Open Loop Clock Frequency45.6048.0049.12MHzNormal Mode (DFLLCTRLA.LOWFREQ=0)
6.768.009.20Low Frequency Mode (DFLLCTRLA.LOWFREQ=1)
DFLL_9DFLL_OL_SRTStart-Up (Ready bit valid)1316µsNormal Mode (DFLLCTRLA.LOWFREQ=0)
6875Low Frequency Mode (DFLLCTRLA.LOWFREQ=1)
DFLL48MHz (Closed Loop) (3,4)
DFLL_11DFLL_CL_FIN (4)DFLL Closed loop Input Frequency Range1000327681000000Hz
DFLL_13DFLL_CL_FOUT (6)DFLL Closed Loop Clock Frequency47.8848.0048.12MHzNormal Mode

(DFLLCTRLA.LOWFREQ=0)

XOSC32 32.768 kHz PPM ≤ 100,

DFLLMUL = 1465

7.988.008.02Low Frequency Mode

(DFLLCTRLA.LOWFREQ=1)

XOSC32 32.768 kHz PPM ≤ 100,

DFLLMUL = 244

DFLL_15DFLL_CL_JitterDFLL Period Jitter Pk-to-Pk0.922.700%Normal Mode

(DFLLCTRLA.LOWFREQ=0)

XOSC32 32.768 kHz PPM ≤ 100,

DFLLMUL = 1465

DFLL_171.02.000%Low Frequency Mode

(DFLLCTRLA.LOWFREQ=1)

XOSC32 32.768 kHz PPM ≤ 100,

DFLLMUL = 244

DFLL_21DFLL_CL_SRT (5, 6)DFLL Closed Loop Mode / Lock Time0.390.900msNormal Mode

(DFLLCTRLA.LOWFREQ=0)

XOSC32 32.768 kHz PPM ≤ 100,

DFLLMUL = 1465

0.331.000Low Frequency Mode

(DFLLCTRLA.LOWFREQ=1)

XOSC32 32.768 kHz PPM ≤ 100,

DFLLMUL = 244

Note:
  1. In Open Loop mode the DFLL uses a self contained internal RC oscillator clock source who's course calibrated value is loaded at out of reset. In addition, there is a fine tune trim register (DFLLTUNE) the user software can assess.
  2. Not recommended for functional USB operation, SOF sync start-up only.
  3. In Closed loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using register DFLLMUL.
  4. To insure that the DFLL stays within the +/-0.25% of its clock frequency, any reference clock for DFLL in close loop must be within a 8% maximum error accuracy.
  5. REFCLK for DFLL or XOSC32K,PLL is XOSC.
  6. DFLLCTRLB.QLDIS = 0: quick lock enabled (default), DFLLCTRLB.CCDIS = 0: chill cycles enabled (default).

    DFLLMUL.STEP = 8 : Max fine step size, divided or dividing into two parts, search 8 is optimum value.

    During a maximum of 30 cycles of the reference clock period (250 cycles for 1Mhz), between lock flag asserted and frequency stabilization, DFLL frequency accuracy will be limited to +/-1.5% at 48Mhz (+/-3% at 8Mhz); after this duration, the frequency accuracy is within +/-0.25%.

    At 1khz reference clock and to maintain the frequency accuracy within +/-0.25% for 48Mhz, a reduced STEP value at 4 (instead of the optimum 8) eliminates this period of inaccuracy, at the expense of maximum 15% of lock time.

Table 51-23. PLL (Frequency Digital Phase Locked Loop) AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
PLLxxMHz (Fractional Digital Phase Locked Loop)
PLL_1PLL_FINPLL Input Frequency Range448MHzOver full voltage and temperature operating ranges
PLL_3PLL_FOUTPLL Output Clock Frequency12.7200MHz
PLL_11PLL_SRT (5) PLL Lock Time25µs
Note:
  1. In Open Loop mode the DFLL uses a self contained internal RC oscillator clock source who's course calibrated value is loaded at out of reset. In addition, there is a fine tune trim register (DFLLTUNE) the user software can assess.
  2. Not recommended for functional USB operation, SOF sync start-up only.
  3. In Closed loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using register DFLLMUL.
  4. To insure that the DFLL stays within the +/-0.25% of its clock frequency, any reference clock for DFLL in close loop must be within a 8% maximum error accuracy.
  5. REFCLK for DFLL or XOSC32K,PLL is XOSC.
  6. DFLLCTRLB.QLDIS = 0: quick lock enabled (default), DFLLCTRLB.CCDIS = 0: chill cycles enabled (default).

    DFLLMUL.STEP = 8: Max fine step size, divided or dividing into two parts, search 8 is optimum value.

    During a maximum of 30 cycles of the reference clock period (250 cycles for 1Mhz), between lock flag asserted and frequency stabilization, DFLL frequency accuracy will be limited to +/-1.5% at 48Mhz (+/-3% at 8Mhz); after this duration, the frequency accuracy is within +/-0.25%.

    At 1khz reference clock and to maintain the frequency accuracy within +/-0.25% for 48Mhz, a reduced STEP value at 4 (instead of the optimum 8) eliminates this period of inaccuracy, at the expense of maximum 15% of lock time.