51.18 DFLL/PLL Electrical Specifications
AC CHARACTERISTICS | Standard
Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
---|---|---|---|---|---|---|---|
Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
DFLL48MHz (Open Loop) (1,2) | |||||||
DFLL_1 | DFLL_OL_FOUT | DFLL Open Loop Clock Frequency | 45.60 | 48.00 | 49.12 | MHz | Normal Mode (DFLLCTRLA.LOWFREQ=0) |
6.76 | 8.00 | 9.20 | Low Frequency Mode (DFLLCTRLA.LOWFREQ=1) | ||||
DFLL_9 | DFLL_OL_SRT | Start-Up (Ready bit valid) | — | 13 | 16 | µs | Normal Mode (DFLLCTRLA.LOWFREQ=0) |
— | 68 | 75 | Low Frequency Mode (DFLLCTRLA.LOWFREQ=1) | ||||
DFLL48MHz (Closed Loop) (3,4) | |||||||
DFLL_11 | DFLL_CL_FIN (4) | DFLL Closed loop Input Frequency Range | 1000 | 32768 | 1000000 | Hz | — |
DFLL_13 | DFLL_CL_FOUT (6) | DFLL Closed Loop Clock Frequency | 47.88 | 48.00 | 48.12 | MHz | Normal Mode (DFLLCTRLA.LOWFREQ=0) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1465 |
7.98 | 8.00 | 8.02 | Low Frequency Mode
(DFLLCTRLA.LOWFREQ=1) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 244 | ||||
DFLL_15 | DFLL_CL_Jitter | DFLL Period Jitter Pk-to-Pk | — | 0.92 | 2.700 | % | Normal Mode (DFLLCTRLA.LOWFREQ=0) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1465 |
DFLL_17 | — | 1.0 | 2.000 | % | Low Frequency Mode
(DFLLCTRLA.LOWFREQ=1) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 244 | ||
DFLL_21 | DFLL_CL_SRT (5, 6) | DFLL Closed Loop Mode / Lock Time | — | 0.39 | 0.900 | ms | Normal Mode (DFLLCTRLA.LOWFREQ=0) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1465 |
— | 0.33 | 1.000 | Low Frequency Mode
(DFLLCTRLA.LOWFREQ=1) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 244 | ||||
Note:
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AC CHARACTERISTICS | Standard
Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
---|---|---|---|---|---|---|---|
Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
PLLxxMHz (Fractional Digital Phase Locked Loop) | |||||||
PLL_1 | PLL_FIN | PLL Input Frequency Range | 4 | — | 48 | MHz | Over full voltage and temperature operating ranges |
PLL_3 | PLL_FOUT | PLL Output Clock Frequency | 12.7 | — | 200 | MHz | |
PLL_11 | PLL_SRT (5) | PLL Lock Time | — | 25 | — | µs | — |
Note:
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