31.4 Signal Interface

The ETH Controller module includes the following signal interfaces:

  • MII and RMII to an external PHY
  • MDIO interface for external PHY management
  • Client APB interface for accessing ETH registers
  • Host AXI interface for memory access
  • TSUCOMP signal for TSU timer count value comparison
Table 31-1. Ethernet MAC Connections in Different Modes
Signal NameFunctionMIIRMII
ETH_TXCK1(1)Transmit Clock or Reference ClockTXCKREFCK
ETH_TXENTransmit EnableTXENTXEN
ETH_TX[7:0]Transmit DataTXD[3:0]TXD[1:0]
ETH_TXERTransmit Coding ErrorTXERNot Used
ETH_RXCKReceive ClockRXCKNot Used
ETH_RXDVReceive Data ValidRXDVCRSDV
ETH_RX[7:0]Receive DataRXD[3:0]RXD[1:0]
ETH_RXERReceive ErrorRXERRXER
ETH_CRSCarrier Sense and Data ValidCRSNot Used
ETH_COLCollision DetectCOLNot Used
ETH_MDCManagement Data ClockMDCMDC
ETH_MDIOManagement Data Input/OutputMDIOMDIO
Note:
  1. Input only. ETH_TXCK1 must be provided with a 25 MHz / 50 MHz clock for MII / RMII interfaces, respectively.